US5252909A
Expired / Lapsed
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Constant-voltage generating circuit
Assignee: NEC Corp
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Filing: 1992-01-23
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Granted: 1993-10-12
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Expires: 2012-01-23
Abstract
Abstract In a constant-voltage generating circuit wherein a first series circuit of PMOS transistors, a second series circuit of a PMOS transistor and an NMOS transistor and a third series circuit of PMOS transistors are connected between a power source line and a ground line, a capacitive element is connected between a common node of the PMOS transistors of the first series circuit and the ground line. In addition to this capacitive element, another capacitive element may be connected between the node and the power source line. Since the node is connected to gates of one of the PMOS transistors of the first series circuit and the PMOS transistor of the second series circuit, the capacitance at this node with respect to the power source line is large. Thus, when the power supply voltage fluctuates abruptly, the voltage at the first node also changes and thus the output voltage also changes. This phenomenon can be suppressed by the action of the capacitive element connected between the common junction node of the first series circuit and the ground line.
Inventors
- 👤 Shingo Aizaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 18:29
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/465; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242; G05F3/247
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
240 words
A constant-voltage generating circuit comprising: a first P-channel MOS transistor (Qp1) having a source connected to a power source line (Vcc) and a gate and a drain both connected to a first node (N1); a second P-channel MOS transistor (Qp2) having a source connected to said first node, a gate connected to a second node, and a drain connected to a ground line; a third P-channel MOS transistor (Qp3) having a source connected to said power source line, a gate connected to said first node, and a drain connected to said second node; a fourth P-channel MOS transistor (Qp4) having a source connected to said power source line, a gate connected to said second node, and a drain connected to an output terminal (V REF ); a current source element (Q N 1) connected between said second node and said ground line; and an impedance element (Q p 5) connected between said output node and said ground line; and a first capacitive element (Q N C) connected between said first node and said ground line for increasing capacitance therebetween wherein the total capacitance between the first node and the power source line divided by the total capacitance between the first node and the ground line is substantially equal to the power source voltage minus an absolute value of a threshold voltage of the P-channel MOS transistor divided by the absolute value of the threshold voltage of the P-channel MOS transistor.
Claim 2
Dependent Claim
240 words
A constant-voltage generating circuit comprising: a first P-channel MOS transistor (Qp1) having a source connected to a power source line (Vcc) and a gate and a drain both connected to a first node (N1); a second P-channel MOS transistor (Qp2) having a source connected to said first node, a gate connected to a second node, and a drain connected to a ground line; a third P-channel MOS transistor (Qp3) having a source connected to said power source line, a gate connected to said first node, and a drain connected to said second node; a fourth P-channel MOS transistor (Qp4) having a source connected to said power source line, a gate connected to said second node, and a drain connected to an output terminal (V REF ); a current source element (Q N 1) connected between said second node and said ground line; and an impedance element (Q p 5) connected between said output node and said ground line; and a first capacitive element (Q N C) connected between said first node and said ground line for increasing capacitance therebetween wherein the total capacitance between the first node and the power source line divided by the total capacitance between the first node and the ground line is substantially equal to the power source voltage minus an absolute value of a threshold voltage of the P-channel MOS transistor divided by the absolute value of the threshold voltage of the P-channel MOS transistor.
Claim 3
Dependent Claim
39 words
A constant-voltage generating circuit according to claim 1, in which said first capacitive element is an N-channel MOS transistor having a gate connected to said first node, and a source and a drain both connected to the ground line.
Claim 4
Dependent Claim
32 words
A constant-voltage generating circuit according to claim 1, which further comprises a second capacitive element (Q p C) connected between said first node and said power source line for increasing capacitance therebetween.
Claim 5
Dependent Claim
70 words
A constant-voltage generating circuit according to claim 3, in which said first capacitive element is an N-channel MOS transistor having a gate connected to said first node, and a source and a drain both connected to the ground line, and said second capacitive elements is a P-channel MOS transistor having a gate connected to said first node, and a source and a drain both connected to said power source line.
Claim 6
Dependent Claim
18 words
A constant-voltage generating circuit according to claim 1, in which said first capacitive element is a junction capacitor.
Claim 7
Dependent Claim
20 words
A constant-voltage generating circuit according to claim 3, in which said first and second capacitive elements are junction capacitors, respectively.
Claim 8
Dependent Claim
43 words
A constant-voltage generating circuit according to claim 1, in which said current source element is an N-channel MOS transistor having a gate connected to said power source line, a drain connected to said second node, and a source connected to said ground line.
Claim 9
Dependent Claim
38 words
A constant-voltage generating circuit according to claim 1, in which said impedance element is a P-channel MOS transistor having a source connected to said output terminal, and a gate and a drain both connected to said ground line.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-10-11 | 1997-04-12 | 1997-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-11 | 2001-04-12 | 2001-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-11 | 2005-04-12 | 2005-10-12 | $7700.00 | Window Closed / Lapsed |