US5260901A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output circuit of semiconductor memory device
Assignee: Mitsubishi Electric Corp
•
Filing: 1991-10-17
•
Granted: 1993-11-09
•
Expires: 2011-10-17
Abstract
Abstract An output circuit for providing data read from a memory cell is disclosed. When a power source is turned on, initial value data set in a register circuit is read and then latched in comparison circuits. The data latched in the comparison circuits are applied through NOR circuits to a plurality of transistors, so that the transistors corresponding in number to the initial value data are rendered conductive. An output signal is fed back from a common output terminal of the respective transistors to the comparison circuits, so that the respective comparison circuits compare between respective threshold values and the output signal. Thus, a determination is made as to whether the gradient of leading edges of waveforms of the output signal is sharp or gradual. If the gradient is gradual, the number of transistors becoming conductive increases, whereas if the gradient is sharp, the number of such transistors decreases. This makes it possible to suppress ringing included in the output signal waveforms independently of the magnitude of a load connected to the output terminal.
Inventors
- 👤 Kouichi Nagase
- 👤 Yutaka Ikeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 00:45
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C7/106
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
201 words
An output circuit of a semiconductor memory device for providing data read from a storage element to an output terminal, comprising: a plurality of switching means having respective outputs commonly connected to said output terminal; determining means for determining the magnitude of a load of said output terminal on the basis of the gradient of leading edges of waveforms of the data provided to said output terminal; and control means responsive to application of the data read from said storage element for rendering ones of said plurality of switching means, corresponding in number to the magnitude of the load determined by said determining means, conductive; wherein said determining means comprises a plurality of comparison means each provided corresponding to said plurality of switching means for comparing between respective reference voltages and respective levels of leading edges of data waveforms output from said output terminal and, if said respective levels of said leading edges exceed corresponding reference voltages, outputting a signal; and said control means comprises gate means each provided corresponding to said plurality of switching means and responsive to application of the data read from said storage element for rendering corresponding switching means conductive if corresponding comparison means output a signal.
Claim 2
Dependent Claim
201 words
An output circuit of a semiconductor memory device for providing data read from a storage element to an output terminal, comprising: a plurality of switching means having respective outputs commonly connected to said output terminal; determining means for determining the magnitude of a load of said output terminal on the basis of the gradient of leading edges of waveforms of the data provided to said output terminal; and control means responsive to application of the data read from said storage element for rendering ones of said plurality of switching means, corresponding in number to the magnitude of the load determined by said determining means, conductive; wherein said determining means comprises a plurality of comparison means each provided corresponding to said plurality of switching means for comparing between respective reference voltages and respective levels of leading edges of data waveforms output from said output terminal and, if said respective levels of said leading edges exceed corresponding reference voltages, outputting a signal; and said control means comprises gate means each provided corresponding to said plurality of switching means and responsive to application of the data read from said storage element for rendering corresponding switching means conductive if corresponding comparison means output a signal.
Claim 3
Dependent Claim
69 words
The output circuit according to claim, 1, further comprising: register means for storing initial value data to be applied to each said comparison means; and means responsive to turning on of a power source for setting the initial value data stored in said register means; and wherein each said gate means comprises means responsive to the initial value data set in said comparison means for controlling corresponding switching means.
Claim 4
Independent Claim
97 words
A method for controlling an output signal of a storage element in a semiconductor memory device using gate elements coupled to an output of the storage element, said method comprising the steps of: determining magnitude of a load coupled to the storage element by comparing the gradient of a leading edge of the output signal with a reference value to form a gating signal, and applying the gating signal and the output of the storage element to at least one of the gate elements to modify the output signal in accordance with the magnitude of the load.
Claim 5
Independent Claim
97 words
A method for controlling an output signal of a storage element in a semiconductor memory device using gate elements coupled to an output of the storage element, said method comprising the steps of: determining magnitude of a load coupled to the storage element by comparing the gradient of a leading edge of the output signal with a reference value to form a gating signal, and applying the gating signal and the output of the storage element to at least one of the gate elements to modify the output signal in accordance with the magnitude of the load.
Claim 6
Dependent Claim
39 words
The method of claim 3, wherein said step of determining comprises comparing the gradient of the leading edge of the output signal with a plurality of various reference signals to form a plurality of components of the gating signal.
Claim 7
Dependent Claim
23 words
The method of claim 4, wherein said step of applying comprises supplying a plurality of the gating elements with the plurality of components.
Claim 8
Dependent Claim
24 words
The method of claim 5, wherein the number of the gating elements activated by the gating signals depends from the magnitude of the load.
References Cited (Backward Citations)
JPS61212116A
Cited
US4719369A
Cited
US4779013A
Cited
US4815113A
Cited
JPS6420721A
Cited
US5142495A
Cited
US5121013A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-08 | 1997-05-10 | 1997-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-08 | 2001-05-10 | 2001-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-08 | 2005-05-10 | 2005-11-09 | $7700.00 | Window Closed / Lapsed |