Dual pipe cache memory with out-of-order issue capability

Claim 2

Cache memory apparatus for storing and loading data in a pipeline computer comprising, in combination: first memory means having a plurality of locations; clock means providing sequential clock cycles; instruction issue means for issuing an instruction stream containing store instructions for controlling storage of data in said first memory means and load instructions for controlling retrieval of data from said first memory means; first cache control means connected to said instruction issue means and to said first memory means, said first cache control means being responsive to a load instruction issued by the instruction issue means to execute the load instruction at a load address in said first memory means, the load address representing a location in said first memory means from where data are to be retrieved under control of the corresponding load instruction, said first cache control means further being responsive to a store instruction issued by the instruction issue means and to a first clock cycle issued by said clock means to allocate a store cycle issued by said clock means to allocate a store address, the store address representing a location in said first memory means where data are to be stored under control of the corresponding store instruction; and store history table means connected to said first cache control means and responsive to the allocation of a store address by said first cache control means to store a record of the store instruction issued by said instruction issue means, said record including the store address allocated by the first cache control means; said first cache control means being responsive to said store history table means and to a second clock cycle subsequent to the first clock cycle to commit the store instruction at the corresponding allocated store address in said first memory means and said store history table means being responsive to the first cache control means committing a store instruction to clear the record of the committed store instruction.

Claim 3

Apparatus according to claim 1 wherein said first cache control means is responsive said instruction issue means and to said store history table means for setting a store conflict condition in response to a load instruction from said instruction issue means for a store address in a record stored in said store history table means, said instruction issue means being responsive to a store conflict condition and to said clock means to reissue the load instruction which caused the store conflict condition during a subsequent clock cycle.

Claim 4

Apparatus according to claim 2 wherein the instruction stream issued by said instruction issue means includes plural branches of instructions, the apparatus further including branch test means for determining whether a branch of instruction is a correct branch or a branch error, said first cache control being further responsive to a determination of a branch error condition by the branch test means to clear store instruction records from said store history table means.

Claim 5

Apparatus according to claim 2 wherein said store history table means is responsive to said first cache control means to assign a unique store identification number to each record of a store instruction stored in said store history table means, said store history table means being responsive to the first cache control means to sequentially circulate through the store identification numbers as said first cache control means allocates store addresses, said store history table means being operable to invalidate all store instruction records upon rollover from the highest store identification number to the lowest store identification number.

Claim 6

Apparatus according to claim 2 wherein said store history table means is responsive to the allocation of a store address by said first cache control means to clear records of store instructions prior in the instruction stream to the store instruction corresponding to the allocated store address.

Claim 7

Apparatus according to claim 2 wherein said first cache control means includes tag means for storing a record of the addresses of data stored in said first memory means, said first cache control means setting a load miss condition in response to a load address from said instruction issue means for an address not stored in said tag means; second memory means; and second cache control means connected to said first cache control means and to said second memory means and responsive to said load miss condition to load data from said second memory means.

Claim 8

Apparatus according to claim 6 wherein said first cache means is further responsive to said store history table means to set said load miss condition is no store conflict condition exists.

Claim 9

Apparatus according to claim 1 further including first pipeline means connected between said instruction issue means and said first cache control means for transmitting store instructions to said first cache control means and second pipeline means connected between said instruction issue means and said first cache control means for transmitting load instructions to said first cache control means.

Claim 10

Apparatus according to claim 1 wherein said instruction issue means operates in accordance with the algorithm comprising: (a) a load instruction corresponding to a given address may be issued in any order in the instruction stream as long as there are no store instructions ahead of the load instruction in the instruction stream having a record in said store history table corresponding to the same given address , and (b) store instructions may be issued in any order.

Claim 11

Apparatus according to claim 1 wherein the instruction stream issued by said instruction issue means includes plural branches of instructions, the apparatus further including branch test means for determining whether a branch of instructions is a correct branch or a branch error, said first cache control being further responsive to a determination of a branch error condition by the branch test means to clear store instruction records from said store history table means.

Claim 12

Apparatus according to claim 10 wherein said store history table means is responsive to said first cache control means to assign a unique store identification number to each record of a store history table means being responsive to the first cache control means to sequentially circulate through the store identification numbers as said first cache control means allocates store addresses, said store history table means being operable to invalidate all store instruction records upon rollover from the highest store identification number to the lowest store identification number.

Claim 13

Apparatus according to claim 1 wherein said store history table means is responsive to said first cache control means to assign a unique store identification number to each record of a store instruction stored in said store history table means, said store history table means being responsive to the first cache control means to sequentially circulate through the store identification numbers as said first cache control means. allocates store addresses, said store history table means being operable to invalidate all store instruction records upon rollover from the highest store identification number to the lowest store identification number.

Claim 14

Apparatus according to claim 1 wherein said first cache control means includes tag means for storing a record of the addresses of data stored in said first memory means, said first cache control means setting a load miss condition in response to a load address in a load instruction from said instruction issue means for an address not stored in said tag means; second memory means; and second cache control means connected to said first cache control means and to said second memory means and responsive to said load miss condition to load data from said second memory means.

Claim 15

Apparatus according to claim 13 wherein said first cache control means is further responsive to said store history table means and to said load address to set said load miss condition if said load address is not an address in a record stored in said store history table means.

Claim 16

Apparatus according to claim 1 wherein said store history table means is responsive to the allocation of a store addresses by said first cache control means to clear records of store instructions prior in the instruction stream to the store instruction corresponding to the allocated store address.

Claim 17

Cache memory apparatus for storing and loading data in a pipeline computer comprising, in combination: first memory means having a plurality of locations; clock means providing sequential clock cycles; instruction issue means for issuing an instruction stream containing store instructions to control storage of data in said first memory means and load instructions to control retrieval of data from said first memory means; first cache control means connected to said instruction issue means and to said first memory means, said first cache control means being responsive to a load instruction issued by the instruction issue means to execute the load instruction at a load address in said first memory means, the load address representing a location in said first memory means from where data are to be retrieved under control of the corresponding load instruction; and store history table means connected to said first cache control means and responsive to a store instruction issued by the instruction issue means and to said clock means to execute a store allocate pass during a first clock cycle and a separate store commit pass during a second clock cycle subsequent to the first clock cycle, said store history table storing a record of the store instruction during a store allocate pass, said record including a store address representing a location in said first memory means where data are to be stored under control of the corresponding store instruction; said first cache control means being responsive to a store instruction issued by said instruction issue means to operate said store history table means to execute said store allocate pass whereby the store address corresponding to the store instruction is reserved, said first cache control further being responsive to a store commit pass to execute the store instruction at the store address in said first memory means, said store history table means being responsive to the first cache control means executing a store instruction to clear the record of the executed store instruction.

Claim 18

Cache memory apparatus for storing and loading data in a pipeline computer comprising, in combination: first memory means having a plurality of locations; clock means providing sequential clock cycles; instruction issue means for issuing an instruction stream containing store instructions to control storage of data in said first memory means and load instructions to control retrieval of data from said first memory means; first cache control means connected to said instruction issue means and to said first memory means, said first cache control means being responsive to a load instruction issued by the instruction issue means to execute the load instruction at a load address in said first memory means, the load address representing a location in said first memory means from where data are to be retrieved under control of the corresponding load instruction; and store history table means connected to said first cache control means and responsive to a store instruction issued by the instruction issue means and to said clock means to execute a store allocate pass during a first clock cycle and a separate store commit pass during a second clock cycle subsequent to the first clock cycle, said store history table storing a record of the store instruction during a store allocate pass, said record including a store address representing a location in said first memory means where data are to be stored under control of the corresponding store instruction; said first cache control means being responsive to a store instruction issued by said instruction issue means to operate said store history table means to execute said store allocate pass whereby the store address corresponding to the store instruction is reserved, said first cache control further being responsive to a store commit pass to execute the store instruction at the store address in said first memory means, said store history table means being responsive to the first cache control means executing a store instruction to clear the record of the executed store instruction.

Claim 19

Apparatus according to claim 16 wherein said first cache control means is responsive to said instruction issue means and to said store history table means for setting a store conflict condition in response to a load instruction from said instruction issue means for a store address in a record in said store history table means, said instruction issue means being responsive to a store conflict condition and to said clock means to reissue the load instruction which caused the store conflict condition during a subsequent clock cycle.

Claim 20

Apparatus according to claim 16 wherein said first cache control means includes tag means for storing a record of the addresses of data stored in said first memory means, said first cache control means setting a load miss condition in response to a load address from said instruction issue means for an address not stored in said tag means; second memory means; and second cache control means connected to said first cache control means and to said second memory means and responsive to said load miss condition to load data from the load address in said second memory means causing the load miss signal.

Claim 21

Apparatus according to claim 18 wherein said first cache means is further responsive to said store history table means and to said load address to set said load miss condition if said load address is not an address in a record stored in said store history table means.

Claim 22

Apparatus according to claim 18 wherein said second cache control means is connected to said first cache control means, and said second cache control means operates said second memory means in an order of priority that (a) store instructions to be executed during store commit passes are accorded highest priority, (b) load instructions that caused miss conditions in the first memory means are accorded a lower priority than store commit passes, and (c) store addresses to be reserved during store allocate passes are accorded a lower priority than load instruction.

Claim 23

Apparatus according to claim 16 further including first pipeline means connected between said instruction issue means and said first cache control means for transmitting store instructions to said first cache control means and second pipeline means connected between said instruction issue means and said first cache control means for transmitting load instructions to said first cache control means.

Claim 24

Apparatus according to claim 16 wherein said instruction issue means operates in accordance with the algorithm comprising: (a) a load instruction corresponding to a given address may be issued in any order in the instruction stream as long as there are no store instructions ahead of the load instruction in the instruction stream having a record in said store history table corresponding to the same given address , and (b) store instructions may be issued in any order.

Claim 25

Apparatus according to claim 16 wherein the instruction stream issued by said instruction issue means includes plural branches of instructions, the apparatus further including branch test means for determining whether a branch of instructions is a correct branch or a branch error, said first cache control being further responsive to a determination of a branch error condition by the branch test means to clear store instruction records from said store history table means.

Claim 26

Apparatus according to claim 16 wherein said first cache control means is responsive to store instructions issued by the instruction issue means and to store allocation passes to allocate store addresses, said store history table means is responsive to said first cache control means to assign a unique store identification number to each record of a store instruction stored in said store history table means, said store history table means being responsive to the first cache control means to sequentially circulate through the store identification numbers as said first cache control means allocates store addresses, said store history table means being operable to invalidate all store instruction records upon rollover from the highest store identification number to the lowest store identification number.

Claim 27

Instruction issue apparatus for conditionally issuing instructions to a cache memory of a pipeline computer comprising, in combination: instruction issue means for issuing an instruction stream containing a plurality of branches of store and load instructions; cache control means connected to said instruction issue means and to said cache memory for allocating store addresses representing locations in said cache memory where data are to be stored and load addresses representing locations in said cache memory from where data are to be retrieved, said cache control means further including branch test means for determining whether a branch of instructions is a correct branch or a branch error; and store history table means connected to said cache control means and to said instruction issue means and responsive to a store instruction from the instruction issue means to store a record of the store instruction issued by said instruction issue means, said record including the store address of said cache memory where data are to be stored under control of the corresponding store instruction; said store history table means being further responsive to said branch test means determining a branch error condition to clear store instruction records from said store history table means.

Claim 28

Instruction issue apparatus for conditionally issuing instructions to a cache memory of a pipeline computer comprising, in combination: instruction issue means for issuing an instruction stream containing a plurality of branches of store and load instructions; cache control means connected to said instruction issue means and to said cache memory for allocating store addresses representing locations in said cache memory where data are to be stored and load addresses representing locations in said cache memory from where data are to be retrieved, said cache control means further including branch test means for determining whether a branch of instructions is a correct branch or a branch error; and store history table means connected to said cache control means and to said instruction issue means and responsive to a store instruction from the instruction issue means to store a record of the store instruction issued by said instruction issue means, said record including the store address of said cache memory where data are to be stored under control of the corresponding store instruction; said store history table means being further responsive to said branch test means determining a branch error condition to clear store instruction records from said store history table means.

Claim 29

Apparatus according to claim 25 wherein said store history table means is responsive to said cache control means to assign a unique store identification number to each record of a store instruction stored in said store history table means, said store history table means being responsive to the cache control means to sequentially circulate through the store identification numbers as said cache control means allocates store addresses, said store history table means being operable to invalidate all store instruction records upon rollover from the highest store identification number to the lowest store identification number.