US5262985A
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Nonvolatile semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1991-02-22
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Granted: 1993-11-16
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Expires: 2011-02-22
Abstract
Abstract A nonvolatile semiconductor memory device according to the present invention comprises a memory cell array composed of a collection of blocks, each block containing memory cells sharing the source or drain, a first region having the memory cell array formed in its surface region, and a control circuit that, in the erase mode, sets the source shared by a plurality of memory cells to be erased in one block at a first potential and the first region at a second potential higher than the GND potential and lower than the first potential, and at the same time, sets the source shared by a plurality of memory cells not to be erased in other blocks at a third potential equal to or higher than the second potential and lower than the first potential.
Inventors
- 👤 Masashi Wada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:18
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/16; H10B41/40; H10B41/42; H10B41/49; H10B41/50
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
150 words
A nonvolatile semiconductor memory device comprising: a memory cell array formed in a substrate and including a collection of blocks, each block containing a plurality of memory cells sharing a common terminal, the common terminal being one of a source and a drain; a first region having a surface region, said plurality of memory cells being formed in said surface region; and a control circuit that, in an erase mode, sets the common terminal of the plurality of memory cells in a block to be erased at a first potential and sets said first region at a second potential higher than a GND potential and lower than said first potential, and at the same time, sets the common terminal of the plurality of memory cells in a block not to be erased at a third potential equal to or higher than said second potential and lower than said first potential.
Claim 2
Dependent Claim
150 words
A nonvolatile semiconductor memory device comprising: a memory cell array formed in a substrate and including a collection of blocks, each block containing a plurality of memory cells sharing a common terminal, the common terminal being one of a source and a drain; a first region having a surface region, said plurality of memory cells being formed in said surface region; and a control circuit that, in an erase mode, sets the common terminal of the plurality of memory cells in a block to be erased at a first potential and sets said first region at a second potential higher than a GND potential and lower than said first potential, and at the same time, sets the common terminal of the plurality of memory cells in a block not to be erased at a third potential equal to or higher than said second potential and lower than said first potential.
Claim 3
Dependent Claim
43 words
The nonvolatile semiconductor memory device according to claim 1, wherein said control circuit sets the common terminal of the plurality of memory cells in the clock to be erased at a potential generated by a high voltage generator circuit formed in the substrate.
Claim 4
Dependent Claim
35 words
The nonvolatile semiconductor memory device according to claim 1, wherein said control circuit sets said first region at the second potential, the second potential being a power supply potential applied from outside of the substrate.
Claim 5
Dependent Claim
41 words
The nonvolatile semiconductor memory device according to claim 1, wherein said control circuit sets the common terminal of the plurality of memory cells in a block not to be erased at a power supply potential supplied from outside of the substrate.
Claim 6
Dependent Claim
20 words
The nonvolatile semiconductor memory device according to claim 1, wherein said first region is a well formed in said substrate.
Claim 7
Dependent Claim
41 words
The nonvolatile semiconductor memory device according to claim 1, wherein said first region includes an epitaxial layer formed on said substrate and separated into a plurality of wells by grooves, each well corresponding to a block of the collection of blocks.
Claim 8
Dependent Claim
56 words
The nonvolatile semiconductor memory device according to claim 1, wherein each memory cell of said plurality of memory cells includes a first insulating film formed on said substrate, a floating gate formed on said first insulating film, a second insulating film formed on said floating gate, and a control gate formed on said second insulating film.
Claim 9
Dependent Claim
86 words
The nonvolatile semiconductor memory device according to claim 1, wherein each memory cell of said plurality of memory cells includes a first insulating film formed on said substrate, a floating gate formed on said first insulating film, a second insulating film formed on said floating gate, a control gate formed on said second insulating film, and a select gate separated from side walls of said floating gate and said control gate with a third insulating film and separated from said substrate with a fourth insulating film.
Claim 10
Dependent Claim
94 words
The nonvolatile semiconductor memory device according to claim 1, wherein each memory cell of said plurality of memory cells includes a first insulating film formed on said substrate, a floating gate formed on said first insulating film to cover a portion of a channel region, a second insulating film formed on said floating gate, and a control gate formed over a remaining portion of said first insulating film over said channel region not covered with said floating gate, said control gate also being formed on said second insulating film to cover said floating gate.
Claim 11
Dependent Claim
84 words
The nonvolatile semiconductor memory device according to claim 1, wherein each memory cell of said plurality of memory cells includes a plurality of memory elements, each memory element of said plurality of memory elements including a first insulating film formed on said substrate, a floating gate formed on said first insulating film, a second insulating film formed on said floating gate, and a control gate formed on said second insulating film, each memory element of said plurality of memory elements being connected in series.
Claim 12
Dependent Claim
152 words
A nonvolatile semiconductor memory device comprising: a memory cell array formed in a substrate and including a collection of blocks, each block containing a plurality of memory cells sharing a common terminal, the common terminal being one of a source and a drain; a first region having a surface region in which one or more blocks of said collection of blocks are formed; and a control circuit that, in an erase mode, sets the common terminal of the plurality of memory cells in a block to be erased at a first potential and sets said first region at a second potential higher than a GND potential and lower than said first potential, and at the same time, sets the common terminal of the plurality of memory cells in a block not to be erased at a third potential equal to or higher than said second potential and lower than said first potential.
Claim 13
Dependent Claim
152 words
A nonvolatile semiconductor memory device comprising: a memory cell array formed in a substrate and including a collection of blocks, each block containing a plurality of memory cells sharing a common terminal, the common terminal being one of a source and a drain; a first region having a surface region in which one or more blocks of said collection of blocks are formed; and a control circuit that, in an erase mode, sets the common terminal of the plurality of memory cells in a block to be erased at a first potential and sets said first region at a second potential higher than a GND potential and lower than said first potential, and at the same time, sets the common terminal of the plurality of memory cells in a block not to be erased at a third potential equal to or higher than said second potential and lower than said first potential.
Claim 14
Dependent Claim
43 words
The nonvolatile semiconductor memory device according to claim 11, wherein said control circuit sets the common terminal of the plurality of memory cells in a block to be erased at a potential generated by a high voltage generator circuit formed in the substrate.
Claim 15
Dependent Claim
35 words
The nonvolatile semiconductor memory device according to claim 11, wherein said control circuit sets said first region at the second potential, the second potential being a power supply potential applied from outside of the substrate.
Claim 16
Dependent Claim
41 words
The nonvolatile semiconductor memory device according to claim 11, wherein said control circuit sets the common terminal of the plurality of memory cells in a block not to be erased at a power supply potential supplied from outside of the substrate.
Claim 17
Dependent Claim
20 words
The nonvolatile semiconductor memory device according to claim 11, wherein said first region is a well formed in said substrate.
Claim 18
Dependent Claim
41 words
The nonvolatile semiconductor memory device according to claim 11, wherein said first region includes an epitaxial layer formed on said substrate and separated into a plurality of wells by grooves, each well corresponding to a block of the collection of blocks.
Claim 19
Dependent Claim
56 words
The nonvolatile semiconductor memory device according to claim 11, wherein each memory cell of said plurality of memory cells includes a first insulating film formed on said substrate, a floating gate formed on said first insulating film, a second insulating film formed on said floating gate, and a control gate formed on said second insulating film.
Claim 20
Dependent Claim
86 words
The nonvolatile semiconductor memory device according to claim 11, wherein each memory cell of said plurality of memory cells includes a first insulating film formed on said substrate, a floating gate formed on said first insulating film, a second insulating film formed on said floating gate, a control gate formed on said second insulating film, and a select gate separated from side walls of said floating gate and said control gate with a third insulating film and separated from said substrate with a fourth insulating film.
Claim 21
Dependent Claim
94 words
The nonvolatile semiconductor memory device according to claim 11, wherein each memory cell of said plurality of memory cells includes a first insulating film formed on said substrate, a floating gate formed on said first insulating film to cover a portion of a channel region, a second insulating film formed on said floating gate, and a control gate formed over a remaining portion of said first insulating film over said channel region not covered with said floating gate, said control gate also being formed ons aid second insulating film to cover said floating gate.
Claim 22
Dependent Claim
84 words
The nonvolatile semiconductor memory device according to claim 11, wherein each memory cell of said plurality of memory cells includes a plurality of memory elements, each memory element of said plurality of memory elements including a first insulating film formed on said substrate, a floating gate formed on said first insulating film, a second insulating film formed on said floating gate, and a control gate formed ons aid second insulating film, each memory element of said plurality of memory elements being connected in series.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-11-15 | 1997-05-17 | 1997-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-15 | 2001-05-17 | 2001-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-15 | 2005-05-17 | 2005-11-16 | $7700.00 | Window Closed / Lapsed |