Diffused buried plate trench dram cell array

Claim 1

A dynamic random access memory device comprising: a semiconductor substrate having a first region of a first conductivity type; at least one array of dynamic memory cells, each cell comprising an access transistor coupled to a storage capacitor, the transistor of each memory cell being formed within a second region of said semiconductor substrate, each access transistor having a control electrode, a data line contact region, a storage node region, and a channel region; a plurality of signal storage capacitors formed in a plurality of trenches in said substrate, each capacitor including a signal storage node region and a reference voltage node region separated by a dielectric insulator, the reference voltage node region being formed on said first region of said substrate and the signal storage node region of each capacitor being connected to a corresponding storage node region of one of said access transistors; means for physically and electrically isolating all of the channel regions of said access transistors within said one array from said first region of said substrate, said isolating means comprising a third region of opposite conductivity type to said first region, said third region formed laterally between said first and second regions, said third region intersecting and extending below the bottom of all of said trenches; said third region comprising said reference voltage node region having a substantially constant impurity doping concentration throughout its depth and said third region comprising an isolation region extending substantially around said array and extending between said reference voltage node region and a surface of said semiconductor substrate; and means for biasing said first, second and third regions of said substrate to first, second and third different reference voltages.