Inherently impedance matched multiple integrated circuit module

Claim 2

An electronic component comprising: a) a substrate having top and bottom sides and having circuit traces thereon; b) active circuitry installed on the substrate and connected to the circuit traces; c) a plurality of connectors connected to the circuit traces; d) the connectors each consisting of a primary conductor and a secondary conductor, wherein the impedance between the primary conductor and the secondary conductor per unit length is a predetermined value; e) the connectors being connectable into a stacked module, whereby said component may be interconnected with additional components which are configured so as to mate with said component so as to form an interconnected stack of plural components, and the plural components may in turn be connected through a bottom component to external circuitry, and wherein connections between said plural components is in a manner such that a plurality of connectors on superjacent substrates, including at least some of said connectors on said component, are vertically aligned.

Claim 3

The electronic component of claim 1, wherein: a) at least one of said plurality of said connectors each consists of a center conductor functioning as the primary conductor and a shield conductor functioning as a secondary conductor; b) the shield conductor surrounds the primary conductor; and c) impedance controlling material is provided between the primary and shield conductors.

Claim 4

The electronic component of claim 2, wherein: a) the substrate has a ground plane thereon; and b) said shield conductors are connected to said ground plane.

Claim 5

The electronic component of claim 2, wherein: a) said impedance controlling material between the primary and shield conductors is a dielectric.

Claim 6

The electronic component of claim 2, wherein: a) said impedance controlling material between the primary and shield conductors is a dielectric; and b) said primary and shield conductors are coaxially arranged.

Claim 7

The electronic component of claim 3, wherein: a) said impedance controlling material between the primary and shield conductors is a dielectric; and b) said primary and shield conductors are coaxially arranged.

Claim 8

The electronic component of claim 1, wherein: a) said circuitry includes a ground plane; and b) said ground plane is connected to said secondary conductors.

Claim 9

The electronic component of claim 1, wherein: the plurality of connectors are arranged in at least two rows.

Claim 10

A stacked multichip module comprising: a) a plurality of individual modules, each having circuit traces thereon, each individual module having a substrate with active circuitry thereon; b) the substrates having top and bottom sides; c) the active circuitry installed on the substrate being connected to the circuit traces; d) the substrates having a plurality of connectors connected to the circuit traces, the connectors each consisting of a primary conductor and a secondary conductor, wherein the impedance between the primary conductor and the secondary conductor per unit length is a predetermined value; and e) the connectors being connectable into a stacked multichip module which includes said plurality of said individual modules, whereby the substrates may be interconnected, and the plural individual modules may in turn be connected through a bottom individual module to external circuitry, and wherein connections between said plural individual modules is in a manner such that multiple ones of said plurality of said connectors on superjacent substrates, including at least some of said connectors on said substrates, are vertically aligned.

Claim 11

A stacked multichip module comprising: a) a plurality of individual modules, each having circuit traces thereon, each individual module having a substrate with active circuitry thereon; b) the substrates having top and bottom sides; c) the active circuitry installed on the substrate being connected to the circuit traces; d) the substrates having a plurality of connectors connected to the circuit traces, the connectors each consisting of a primary conductor and a secondary conductor, wherein the impedance between the primary conductor and the secondary conductor per unit length is a predetermined value; and e) the connectors being connectable into a stacked multichip module which includes said plurality of said individual modules, whereby the substrates may be interconnected, and the plural individual modules may in turn be connected through a bottom individual module to external circuitry, and wherein connections between said plural individual modules is in a manner such that multiple ones of said plurality of said connectors on superjacent substrates, including at least some of said connectors on said substrates, are vertically aligned.

Claim 12

The stacked multichip module of claim 9, wherein: a) at least one of said plurality of said connectors each consists of a center conductor functioning as the primary conductor and a shield conductor functioning as a secondary conductor; b) the shield conductor surrounds the primary conductor; and c) impedance controlling material is provided between the primary and shield conductors.

Claim 13

The stacked multichip module of claim 10, wherein: a) the substrate has a ground plane thereon; and b) said shield conductors are connected to said ground plane.

Claim 14

The stacked multichip module of claim 10, wherein: a) said impedance controlling material between the primary and shield conductors is a dielectric.

Claim 15

The stacked multichip module of claim 10, wherein: a) said impedance controlling material between the primary and shield conductors is a dielectric; and b) said primary and shield conductors are coaxially arranged.

Claim 16

The stacked multichip module of claim 11, wherein: a) said impedance controlling material between the primary and shield conductors is a dielectric; and b) said primary and shield conductors are coaxially arranged.

Claim 17

The stacked multichip module of claim 9, wherein: a) said circuitry includes a ground plane; and b) said ground plane is connected to said secondary conductors.

Claim 18

The stacked multichip module of claim 9, wherein: the plurality of connectors are arranged in at least two rows.

Claim 19

A stacked multichip module for video signal processing, the stacked multichip module comprising: a) a plurality of individual modules, each having circuit traces thereon, each individual module having a substrate with active circuitry thereon; b) the substrates having top and bottom sides; c) the active circuitry installed on the substrate being connected to the circuit traces; d) the substrates each having a plurality of connectors connected to the circuit traces, the connectors each consisting of a primary conductor and a secondary conductor, wherein the impedance between the primary conductor and the secondary conductor per unit length is a predetermined value; e) the connectors being connectable into said stacked multichip module which includes said plurality of individual modules, whereby the substrates may be interconnected, and wherein connections between said plural individual modules is in a manner such that multiple ones of said plurality of said connectors on superjacent substrates are vertically aligned; and f) at least one of said modules including a video address circuit, the video address circuit receiving signals through the connectors and providing an output in the form of bit mapped signals.

Claim 20

A stacked multichip module for video signal processing, the stacked multichip module comprising: a) a plurality of individual modules, each having circuit traces thereon, each individual module having a substrate with active circuitry thereon; b) the substrates having top and bottom sides; c) the active circuitry installed on the substrate being connected to the circuit traces; d) the substrates each having a plurality of connectors connected to the circuit traces, the connectors each consisting of a primary conductor and a secondary conductor, wherein the impedance between the primary conductor and the secondary conductor per unit length is a predetermined value; e) the connectors being connectable into said stacked multichip module which includes said plurality of individual modules, whereby the substrates may be interconnected, and wherein connections between said plural individual modules is in a manner such that multiple ones of said plurality of said connectors on superjacent substrates are vertically aligned; and f) at least one of said modules including a video address circuit, the video address circuit receiving signals through the connectors and providing an output in the form of bit mapped signals.

Claim 21

The stacked multichip module of claim 17, wherein: a) at least one of said plurality of said connectors each consists of a center conductor functioning as the primary conductor and a shield conductor functioning as a secondary conductor; b) the shield conductor surrounds the primary conductor; and c) impedance controlling material is provided between the primary and shield conductors.

Claim 22

The stacked multichip module of claim 18, wherein: a) the substrate has a ground plane thereon; and b) said shield conductors are connected to said ground plane.

Claim 23

The stacked multichip module of claim 18, wherein: said impedance controlling material between the primary and shield conductors is a dielectric.

Claim 24

The stacked multichip module of claim 18, wherein: a) said impedance controlling material between the primary and shield conductors is a dielectric; and b) said primary and shield conductors are coaxially arranged.

Claim 25

The stacked multichip module of claim 19, wherein: a) said impedance controlling material between the primary and shield conductors is a dielectric; and b) said primary and shield conductors are coaxially arranged.

Claim 26

The stacked multichip module of claim 17, wherein: a) said circuitry includes a ground plane; and b) said ground plane is connected to said secondary conductors.

Claim 27

The stacked multichip module of claim 17, wherein: the plurality of connectors are arranged in at least two rows.