TTL to CMOS input buffer using CMOS structure

Claim 1

A buffer circuit comprising: a TTL output buffer; a CMOS logic gate circuit; said CMOS logic gate circuit including a plurality of first transistors having a CMOS logic structure and having respective transistor current paths connected in series, said CMOS logic gate circuit further including a MOS transistor having another current path connected in series with said respective current paths of said first transistors to control a logic gate threshold voltage of said CMOS logic gate circuit, the plurality of first transistors and said MOS transistor being connected between two power source electrodes, at least one gate input terminal commonly connected to the gate electrodes of at least two of said first transistors and receiving a signal from the TTL output buffer, an output terminal provided from a junction between the series connected current paths of two of said first transistors; a logic threshold voltage of said CMOS logic gate circuit being controlled by a gate voltage of said MOS transistor such that the logic threshold voltage coincides with a predetermined logic threshold voltage substantially independent of any variation in the power supply voltage, temperature, or manufacturing process; and a control circuit for controlling the gate voltage applied to said MOS transistor, wherein said control circuit comprises a dummy CMOS logic gate circuit including another MOS transistor for controlling a threshold voltage of said dummy CMOS logic gate circuit, the dummy CMOS logic gate circuit and the logic gate circuit being structured to be substantially the same with the gates of said MOS transistor and said other MOS transistor being interconnected, and a feedback circuit for amplifying an output of said dummy CMOS logic gate circuit from its output terminal and for feeding an amplified output back to the gate of said other MOS transistor for controlling said CMOS logic gate circuit and said dummy CMOS logic gate circuit.