Abstract A semiconductor read only memory with hierarchical bit lines in which a resistance against a discharge current is constant irrespective of the position of a memory cell from which information is to be read is disclosed. A bank selecting MOSFET is connected to one end portion of a sub-bit line. Another bank selecting MOSFET is connected to the other end portion of the adjacent sub-bit line. Bank selecting MOSFETs are connected in the same alternate manner as described above. Therefore, since the resistance on bit lines against the read-out current is constant, a larger read-out current can be used especially when diffusion bit lines are used, whereby the semiconductor read only memory of the invention can achieve a high-speed read operation.
A semiconductor read only memory comprising: a plurality of first bit lines; a plurality of groups of memory cells, in each group, memory cells being electrically connected in parallel between two adjacent ones of said first bit lines; second bit lines, the proportion of said second bit lines to said first bit lines being 1 to 2; a group of first bank selecting switches each of which is connected between one end of an odd-numbered one of said first bit lines and one end of an odd-numbered one of said second bit liens; and a group of second bank selecting switches each of which is connected between one end of an even-numbered one of said first bit lines and one end of an even-numbered one of said second bit lines.
Claim 2
Dependent Claim
130 words
A semiconductor read only memory comprising: a plurality of first bit lines; a plurality of groups of memory cells, in each group, memory cells being electrically connected in parallel between two adjacent ones of said first bit lines; second bit lines, the proportion of said second bit lines to said first bit lines being 1 to 2; a group of first bank selecting switches each of which is connected between one end of an odd-numbered one of said first bit lines and one end of an odd-numbered one of said second bit liens; and a group of second bank selecting switches each of which is connected between one end of an even-numbered one of said first bit lines and one end of an even-numbered one of said second bit lines.
Claim 3
Dependent Claim
47 words
A semiconductor read only memory according to claim 1, wherein said groups of first and second bank selecting switches are constructed using a plurality of pairs of two adjacent selecting switches, said adjacent two selecting switches being connected to the same one of said second bit lines.
Claim 4
Dependent Claim
19 words
A semiconductor read only memory according to claim 1, wherein said memory cells and said selecting switches are MOSFETs.
Claim 5
Dependent Claim
27 words
A semiconductor read only memory according to claim 1, wherein said first bit liens are made by diffusion layers, and said second bit lines are metal lines.