Semiconductor memory device

Claim 2

A semiconductor memory device having a plurality of bit lines, and a plurality of memory cells connected to the bit lines, the semiconductor memory device comprising: a plurality of control circuits outputting a plurality of control signals; a first control line formed by a first low resistance conductive layer, the first low resistance conductive layer being formed on a substrate forming the plurality of control circuits, the first control line connected to a first control circuit of the plurality of control circuits to transfer the first control signal and extending in a first direction; a second control line formed by a second low resistance conductive layer, the second low resistance conductor layer being formed on the substrate and being separated from the first conductive layer by an insulating layer, the second control line connected to a second control circuit of the plurality of control circuits to transfer the second control signal and extending in a second direction which is substantially different from the first direction.

Claim 3

A semiconductor memory device according to claim 1, wherein the first and second control signals are formed on layers overlapped with each other.

Claim 4

A semiconductor memory device according to claim 1, wherein said plurality of control circuits include a row decoder, a transfer gate control circuit and an equalizing control circuit.

Claim 5

A semiconductor memory device according to claim 1, wherein the first low resistance conductive layer is an aluminum layer.

Claim 6

A semiconductor memory device according to claim 1, wherein the second low resistance conductive layer is an aluminum layer.

Claim 7

A semiconductor memory device according to claim 1, wherein the first direction is substantially perpendicular to the second direction.

Claim 8

A semiconductor memory device comprising: a plurality of memory cell arrays, each having a plurality of memory cells, each memory cell having a cell transistor and a capacitor; a plurality of pairs of bit lines, each of the pairs having a first and a second bit line, each bit line having a first end and a second end, the memory cell connected to the first bit line, and a plurality of word lines connected to gates of the cell transistors; a plurality of sense amplifiers each of which have a first sense amplifier node and a second sense amplifier node and a control terminal; a transfer gate control circuit having a first control line; a plurality of transfer gate transistors each of which is connected between the first end of a bit line and the first sense amplifier node to control the connection thereof, a gate of the transfer transistor connected to the first control line; an equalizing control circuit having a second control line; a plurality of equalizing transistors each of which is connected between the second end of each bit line of each pair of bit lines to control the connection thereof, a gate of the equalizing transistor connected to the second control line; and a row decoder having an input line for receiving a row address buffer output signal, the row decoder connected the plurality of word lines; wherein the first and second control lines each are formed by a first low resistance conductive layer, the first low resistance conductive layer is formed on a substrate having the plurality of memory cells and the input line is formed by a second low resistance conductive layer formed on the substrate and separated from the first conductive layer by an insulating layer.

Claim 9

A semiconductor memory device comprising: a plurality of memory cell arrays, each having a plurality of memory cells, each memory cell having a cell transistor and a capacitor; a plurality of pairs of bit lines, each of the pairs having a first and a second bit line, each bit line having a first end and a second end, the memory cell connected to the first bit line, and a plurality of word lines connected to gates of the cell transistors; a plurality of sense amplifiers each of which have a first sense amplifier node and a second sense amplifier node and a control terminal; a transfer gate control circuit having a first control line; a plurality of transfer gate transistors each of which is connected between the first end of a bit line and the first sense amplifier node to control the connection thereof, a gate of the transfer transistor connected to the first control line; an equalizing control circuit having a second control line; a plurality of equalizing transistors each of which is connected between the second end of each bit line of each pair of bit lines to control the connection thereof, a gate of the equalizing transistor connected to the second control line; and a row decoder having an input line for receiving a row address buffer output signal, the row decoder connected the plurality of word lines; wherein the first and second control lines each are formed by a first low resistance conductive layer, the first low resistance conductive layer is formed on a substrate having the plurality of memory cells and the input line is formed by a second low resistance conductive layer formed on the substrate and separated from the first conductive layer by an insulating layer.

Claim 10

A semiconductor memory device according to claim 7, wherein the semiconductor device further comprises a plurality of sense amplifier control lines and the control terminals of the sense amplifiers connected to the bit lines in the same memory cell array are connected to the same sense amplifier control line.

Claim 11

A semiconductor memory device according to claim 7, wherein each sense amplifier of the plurality of sense amplifiers has a first transistor including a source connected to the first node, a gate connected to the second node and a drain connected to the control terminal, and a second transistor including a source connected to the second node, a gate connected to the first node, and a drain connected to the control terminal.

Claim 12

A semiconductor memory device according to claim 7, wherein the first low resistance conductive layer is an aluminum layer.

Claim 13

A semiconductor memory device according to claim 7, wherein the second low resistance conductive layer is an aluminum layer.

Claim 14

A semiconductor memory device according to claim 7, wherein the first and second control lines extend in a first direction, and the input line extends in a second direction which is substantially different from the first direction.

Claim 15

A semiconductor memory device according to claim 12, wherein the first and second conductive layers are overlapped with each other.

Claim 16

A semiconductor memory device according to claim 12, wherein the first direction is substantially perpendicular to the second direction.