Fast sense amplifier

Claim 2

An integrated circuit sense amplifier comprising: timing signal input means for receiving one or more timing signals; a pair of complementary inputs for receiving a complementary pair of data signals; an output circuit having a pair of complementary outputs wherein the complementary outputs are electrically separate from the complementary inputs; input precharge means responsive to said timing signal for creating a signal level on said complementary inputs near the expected signal levels of said complementary data signals prior to the arrival of said complementary data signals; a preamplifier coupled to said complementary inputs and having a pair of preamplifier outputs, and including means for preamplifying said complementary data signals to produce a complementary pair of preamplifier output signals on said preamplifier outputs, wherein said preamplifier output signals are less than full logic signals; and latch means responsive to said preamplifier output signals for producing a full logic output signal.

Claim 3

An integrated circuit sense amplifier as in claim 1 wherein said input precharge means further comprises means for clamping said complementary inputs to the same signal level prior to the arrival of said complementary data signals.

Claim 4

An integrated circuit sense amplifier comprising: timing signal input means for receiving one or more timing signals; a pair of complementary inputs for receiving a complementary pair of data signals; input precharge means responsive to said timing signal for creating a signal level on said complementary inputs near the expected signal levels of said complementary data signals prior to the arrival of said complementary data signals; latch means responsive to said complementary data signals for producing a full logic output signal a preamplifier located between said complementary inputs and said latch means, having a pair of preamplifier outputs, and including means for preamplifying said complementary data signals to produce a complementary pair of preamplifier output signals on said preamplifier outputs; and preamplifier output precharge means responsive to said timing signal for creating a signal level on said preamplifier outputs between the expected signal levels of said complementary preamplifier output signals prior to the arrival of said complementary data signals.

Claim 5

An integrated circuit sense amplifier comprising: timing signal input means for receiving one or more timing signals; a pair of complementary inputs for receiving a complementary pair of data signals; input precharge means responsive to said timing signal for creating a signal level on said complementary inputs near the expected signal levels of said complementary data signals prior to the arrival of said complementary data signals; latch means responsive to said complementary data signals for producing a full logic output signal a preamplifier located between said complementary inputs and said latch means, having a pair of preamplifier outputs, and including means for preamplifying said complementary data signals to produce a complementary pair of preamplifier output signals on said preamplifier outputs; and preamplifier output precharge means responsive to said timing signal for creating a signal level on said preamplifier outputs between the expected signal levels of said complementary preamplifier output signals prior to the arrival of said complementary data signals.

Claim 6

An integrated circuit sense amplifier as in claim 3 wherein said preamplifier output precharge means further comprises means for clamping said complementary preamplifier outputs to the same signal level prior to the arrival of said complementary data signals.

Claim 7

An integrated circuit as in claim 3 and wherein said timing signals define a signal sense period and further including preamplifier output current control means responsive to said timing signal for preventing current from flowing in said preamplifier at a time not within said signal sense period.

Claim 8

An integrated circuit sense amplifier as in claim 1 wherein said latch means has a pair of complementary latch nodes and further comprises means for latching one latch node at a high signal level appropriate for driving an output circuit and for latching the other latch node at a low signal level appropriate for driving said output circuit.

Claim 9

An integrated circuit sense amplifier comprising: timing signal input means for receiving one or more timing signals; a pair of complementary inputs for receiving a complementary pair of data signals; input precharge means responsive to said timing signal for creating a signal level on said complementary inputs near the expected signal levels of said complementary data signals prior to the arrival of said complementary data signals; latch means responsive to said complementary data signals for producing a full logic output signal, wherein said latch means has a pair of complementary latch nodes and further comprises means for latching one latch node at a high signal level appropriate for driving an output circuit and for latching the other latch node at a low signal level appropriate for driving said output circuit; and a tristate output circuit for utilizing the signals on said latch nodes to produce a complementary pair of tristate output signals.

Claim 10

An integrated circuit sense amplifier comprising: timing signal input means for receiving one or more timing signals; a pair of complementary inputs for receiving a complementary pair of data signals; input precharge means responsive to said timing signal for creating a signal level on said complementary inputs near the expected signal levels of said complementary data signals prior to the arrival of said complementary data signals; latch means responsive to said complementary data signals for producing a full logic output signal, wherein said latch means has a pair of complementary latch nodes and further comprises means for latching one latch node at a high signal level appropriate for driving an output circuit and for latching the other latch node at a low signal level appropriate for driving said output circuit; and a tristate output circuit for utilizing the signals on said latch nodes to produce a complementary pair of tristate output signals.

Claim 11

An integrated circuit sense amplifier as in claim 7 wherein said tristate output circuit comprises a pair of complementary output terminals and tristate output precharge means responsive to said timing signal for creating a signal level on said complementary output terminals between the expected signal levels of said complementary pair of tristate output signals prior to the time said complementary data signals have separated sufficiently to latch said latch means.

Claim 12

An integrated circuit sense amplifier as in claim 8 wherein said tristate output precharge means further comprises means for clamping said complementary output terminals to the same signal level prior to the time said complementary data signals have separated sufficiently to latch said latch means.

Claim 13

An integrated circuit sense amplifier comprising: timing signal input means for receiving one or more timing signals; a pair of complementary inputs for receiving a complementary pair of data signals; input precharge means responsive to said timing signal for creating a signal level on said complementary inputs near the expected signal levels of said complementary data signals prior to the arrival of said complementary data signals; latch means responsive to said complementary data signals for producing a full logic output signal, wherein said latch means has a pair of complementary latch nodes and further comprises means for latching one latch node at a high signal level appropriate for driving an output circuit and for latching the other latch node at a low signal level appropriate for driving said output circuit; and latch node precharge means responsive to said timing signal for creating a signal level on said complementary latch nodes between said high and low signal levels prior to the time said complementary data signals have separated sufficiently to latch said latch means.

Claim 14

An integrated circuit sense amplifier comprising: timing signal input means for receiving one or more timing signals; a pair of complementary inputs for receiving a complementary pair of data signals; input precharge means responsive to said timing signal for creating a signal level on said complementary inputs near the expected signal levels of said complementary data signals prior to the arrival of said complementary data signals; latch means responsive to said complementary data signals for producing a full logic output signal, wherein said latch means has a pair of complementary latch nodes and further comprises means for latching one latch node at a high signal level appropriate for driving an output circuit and for latching the other latch node at a low signal level appropriate for driving said output circuit; and latch node precharge means responsive to said timing signal for creating a signal level on said complementary latch nodes between said high and low signal levels prior to the time said complementary data signals have separated sufficiently to latch said latch means.

Claim 15

An integrated circuit sense amplifier as in claim 10 and further including output current control means responsive to said timing signal for placing said latch nodes in a low current state.

Claim 16

An integrated circuit sense amplifier as in claim 11 wherein said output current control means comprises means for holding said latch nodes at a low logic level whenever said latch output precharge means is not operating and said complementary data signals are not being amplified.

Claim 17

An integrated circuit sense amplifier comprising: timing signal input means for receiving one or more timing signals; a pair of complementary inputs for receiving a pair of complementary data signals; an output circuit having a pair of complementary outputs wherein the complementary outputs are electrically separate from the complementary inputs; latch means having a pair of complementary latch nodes and responsive to said complementary data signals for latching one latch node at a high signal level appropriate for driving said output circuit and for latching the other latch node at a low signal level appropriate for driving said output circuit; and latch node precharge means responsive to said timing signal for creating a signal level on said complementary latch nodes between said high and low signal levels prior to the time said complementary data signals have separated sufficiently to latch said latch means.

Claim 18

An integrated circuit sense amplifier comprising: timing signal input means for receiving one or more timing signals; a pair of complementary inputs for receiving a pair of complementary data signals; an output circuit having a pair of complementary outputs wherein the complementary outputs are electrically separate from the complementary inputs; latch means having a pair of complementary latch nodes and responsive to said complementary data signals for latching one latch node at a high signal level appropriate for driving said output circuit and for latching the other latch node at a low signal level appropriate for driving said output circuit; and latch node precharge means responsive to said timing signal for creating a signal level on said complementary latch nodes between said high and low signal levels prior to the time said complementary data signals have separated sufficiently to latch said latch means.

Claim 19

An integrated circuit sense amplifier comprising: timing signal input means for receiving one or more timing signals; a pair of complementary inputs for receiving a pair of complementary data signals; latch means having a pair of complementary latch nodes and responsive to said complementary data signals for latching one latch node at a high signal level appropriate for driving an output circuit and for latching the other latch node at a low signal level appropriate for driving said output circuit; and latch node precharge means responsive to said timing signal for creating a signal level on said complementary latch nodes between said high and low signal levels prior to the time said complementary data signals have separated sufficiently to latch said latch means; and output current control means responsive to said timing signal for placing said latch nodes in a low current state.

Claim 20

An integrated circuit sense amplifier comprising: timing signal input means for receiving one or more timing signals; a pair of complementary inputs for receiving a pair of complementary data signals; latch means having a pair of complementary latch nodes and responsive to said complementary data signals for latching one latch node at a high signal level appropriate for driving an output circuit and for latching the other latch node at a low signal level appropriate for driving said output circuit; and latch node precharge means responsive to said timing signal for creating a signal level on said complementary latch nodes between said high and low signal levels prior to the time said complementary data signals have separated sufficiently to latch said latch means; and output current control means responsive to said timing signal for placing said latch nodes in a low current state.

Claim 21

An integrated circuit sense amplifier as in claim 14 wherein said output current control means comprises means for holding said latch outputs at a logic low level whenever said latch output precharge means is not operating and said complementary data signals are not being amplified.

Claim 22

An integrated circuit sense amplifier comprising: timing signal input means for receiving one or more timing signals; a pair of complementary inputs for receiving a pair of complementary data signals; latch means having a pair of complementary latch nodes and responsive to said complementary data signals for latching one latch node at a high signal level appropriate for driving an output circuit and for latching the other latch node at a low signal level appropriate for driving said output circuit, wherein said latch means comprises a flip-flop having a high side and a low side, and said node precharge means comprises a pull up transistor connected between said high side of said flip-flop and a source of a logic high voltage, the gate of said pull up transistor being controlled by said timing signal; and latch node precharge means responsive to said timing signal for creating a signal level on said complementary latch nodes between said high and low signal levels prior to the time said complementary data signals have separated sufficiently to latch said latch means.

Claim 23

An integrated circuit sense amplifier comprising: timing signal input means for receiving one or more timing signals; a pair of complementary inputs for receiving a pair of complementary data signals; latch means having a pair of complementary latch nodes and responsive to said complementary data signals for latching one latch node at a high signal level appropriate for driving an output circuit and for latching the other latch node at a low signal level appropriate for driving said output circuit, wherein said latch means comprises a flip-flop having a high side and a low side, and said node precharge means comprises a pull up transistor connected between said high side of said flip-flop and a source of a logic high voltage, the gate of said pull up transistor being controlled by said timing signal; and latch node precharge means responsive to said timing signal for creating a signal level on said complementary latch nodes between said high and low signal levels prior to the time said complementary data signals have separated sufficiently to latch said latch means.

Claim 24

An integrated circuit sense amplifier comprising: timing signal means for receiving timing signals defining a signal sense period; a pair of complementary inputs for receiving a pair of complementary data signals; an output enable circuit including one or more first output enable transistors and one or more second output enable transistors, the gates of said first and second output enable transistors connected to said timing signal means; a latch means responsive to said complementary data signals for providing a complementary pair of latched output signals, said latch means comprising a first p-channel transistor in series with a first n-channel transistor and a second p-channel transistor in series with a second n-channel resistor, the connection between said first p-channel transistor and said first n-channel transistor defining a first latch node and the connection between said second p-channel transistor and said second n-channel transistor defining a second latch node, the sources of said n-channel transistors connected to a logic low voltage, the sources of said p-channel transistors connected to a logic high voltage through a first output enable transistor, the first and second latch nodes connected to a logic low voltage through a second output enable transistor, and said timing signal means further comprising means for turning said one or more first output enable transistors on at a time outside said signal sense period, for turning said one or more first output enable transistors off at the initiation of said sense period, for turning said one or more second output enable transistors off at a time outside said sense period, and for turning said one or more second output enable transistors on at the initiation of said sense period.

Claim 25

An integrated circuit sense amplifier comprising: timing signal means for receiving timing signals defining a signal sense period; a pair of complementary inputs for receiving a pair of complementary data signals; an output enable circuit including one or more first output enable transistors and one or more second output enable transistors, the gates of said first and second output enable transistors connected to said timing signal means; a latch means responsive to said complementary data signals for providing a complementary pair of latched output signals, said latch means comprising a first p-channel transistor in series with a first n-channel transistor and a second p-channel transistor in series with a second n-channel resistor, the connection between said first p-channel transistor and said first n-channel transistor defining a first latch node and the connection between said second p-channel transistor and said second n-channel transistor defining a second latch node, the sources of said n-channel transistors connected to a logic low voltage, the sources of said p-channel transistors connected to a logic high voltage through a first output enable transistor, the first and second latch nodes connected to a logic low voltage through a second output enable transistor, and said timing signal means further comprising means for turning said one or more first output enable transistors on at a time outside said signal sense period, for turning said one or more first output enable transistors off at the initiation of said sense period, for turning said one or more second output enable transistors off at a time outside said sense period, and for turning said one or more second output enable transistors on at the initiation of said sense period.