Semiconductor memory device

Claim 2

A semiconductor memory device comprising a memory cell array including a plurality of word lines, a plurality of first bit lines arranged to cross said word lines and a plurality of memory cells arranged at crossings of said word lines and said bit lines; said device further comprising a plurality of second bit lines arranged to cross said first bit lines, each said second bit line being directly connected to corresponding one of said first bit lines so as to establish an interconnection node common to said second and corresponding first bit lines and having one end extended to an end portion of said memory cell array.

Claim 3

A semiconductor memory device according to claim 1, wherein said second bit lines are arranged parallel to each other.

Claim 4

A semiconductor memory device according to claim 2, wherein said second bit lines are arranged perpendicular to said bit lines.

Claim 5

A semiconductor memory device according to claim 1, wherein said second bit lines are arranged parallel to said word lines.

Claim 6

A semiconductor memory device according to claim 1, wherein intervals between said second bit lines are larger than intervals between said first bit lines.

Claim 7

A semiconductor memory device according to claim 1, further comprising word line selecting means for selecting said word lines, wherein each said second bit line has said one end extended to said end portion of said memory cell array on a side opposite to said word line selecting means.

Claim 8

A semiconductor memory device according to claim 6, wherein said device is housed in an approximately rectangular package having at one end address data IO pins and at another rend IO pins for read/write data and control data.

Claim 9

A semiconductor memory device according to claim 1, further comprising word line selection means for selecting said word lines, wherein each said second bit line has said one end extended to said end portion of said memory cell array on the same side as said word line selecting means.

Claim 10

A semiconductor memory device according to claim 8, wherein said device is housed in an approximately rectangular package having all of signal IO pins formed at one end surface.

Claim 11

A semiconductor memory device according to claim 1, wherein a plurality of said second bit lines are provided for each of said first bit lines.

Claim 12

A semiconductor memory device according to claim 1, wherein said memory cell array is divided into a plurality of blocks arranged in a direction of said bit line, and said second bit lines are provided for each of said divided memory cell array blocks.

Claim 13

A semiconductor memory device according to claim 11, wherein a bit line peripheral circuit coupled to said first bit lines in each of said memory cell array blocks are arranged between said divided memory cell array blocks.

Claim 14

A semiconductor memory device according to claim 1, wherein said memory cells are static memory cells performing static storage of information.

Claim 15

A semiconductor memory device according to claim 1, wherein said memory cells are dynamic memory cells performing a dynamic storage of information.

Claim 16

A semiconductor memory device comprising a plurality of memory cell arrays, each of which includes a plurality of word lines, a plurality of first bit lines arranged to cross said word lines and a plurality of memory cells arranged at crossings of said word lines and said first bit lines; said device further comprising a plurality of second bit lines which are arranged to cross said first bit lines in said respective memory cell arrays for connecting corresponding said first bit lines to each other in said respective memory cell arrays, said second bit lines being directly connected to said first bit lines so as to establish an interconnecting node common to said second and corresponding first bit lines.

Claim 17

A semiconductor memory device comprising a plurality of memory cell arrays, each of which includes a plurality of word lines, a plurality of first bit lines arranged to cross said word lines and a plurality of memory cells arranged at crossings of said word lines and said first bit lines; said device further comprising a plurality of second bit lines which are arranged to cross said first bit lines in said respective memory cell arrays for connecting corresponding said first bit lines to each other in said respective memory cell arrays, said second bit lines being directly connected to said first bit lines so as to establish an interconnecting node common to said second and corresponding first bit lines.

Claim 18

A semiconductor memory device according to claim 15, wherein said second bit lines are parallel to each other.

Claim 19

A semiconductor memory device according to claim 16, wherein said second bit lines are arranged perpendicular to said first bit lines in each of said memory cell arrays.

Claim 20

A semiconductor memory device according to claim 15, wherein said second bit lines are arranged parallel to said word lines in each or said memory cell arrays.

Claim 21

A semiconductor memory device according to claim 15, wherein intervals between said second bit lines are larger than intervals between said first bit lines.

Claim 22

A semiconductor memory device according to claim 15, wherein a plurality of said second bit lines are provided for each of said first bit lines.

Claim 23

A semiconductor memory device according to claim 15, wherein a bit line peripheral circuit is arranged between respective memory cell array, and said second bit lines connect the corresponding first bit lines in said memory cell arrays to each other through said bit line peripheral circuit.

Claim 24

A semiconductor memory device according to claim 15, wherein said memory cell array is divided into a plurality of blocks arranged in a direction of said first bit line, and said second bit lines are provided for each of said divided memory cell array blocks.

Claim 25

A semiconductor memory device according to claim 22, wherein a bit line peripheral circuit coupled to said first bit lines in said respective memory cell array blocks is disposed between said divided memory cell array blocks.

Claim 26

A semiconductor memory device according to claim 15, wherein said memory cells are static memory cells performing static storage of information.

Claim 27

A semiconductor memory device according to claim 15, wherein said memory cells are dynamic memory cells performing dynamic storage of information.

Claim 28

A semiconductor memory device comprising a memory cell array including a plurality of word lines, a plurality of first bit lines arranged to cross said word lines and a plurality of memory cells arranged at crossings of said word lines and said first bit lines; said device further comprising: a plurality of second bit lines arranged to cross said first bit lines and connected to corresponding said first bit lines, each having at least one end extended to an end of said memory cell array, said second bit lines being directly connected to said first bit lines so as to establish interconnection node common to said second and corresponding first bit lines; a bit line peripheral circuit arranged at said one end of said memory cell array and coupled to said second bit lines; IO means for inputting external data and/or a signal from and for outputting an internal signal and/or data to the external; and IO lines arranged to cross said memory cell array and to couple said bit line peripheral circuit and the IO means with each other.

Claim 29

A semiconductor memory device comprising a memory cell array including a plurality of word lines, a plurality of first bit lines arranged to cross said word lines and a plurality of memory cells arranged at crossings of said word lines and said first bit lines; said device further comprising: a plurality of second bit lines arranged to cross said first bit lines and connected to corresponding said first bit lines, each having at least one end extended to an end of said memory cell array, said second bit lines being directly connected to said first bit lines so as to establish interconnection node common to said second and corresponding first bit lines; a bit line peripheral circuit arranged at said one end of said memory cell array and coupled to said second bit lines; IO means for inputting external data and/or a signal from and for outputting an internal signal and/or data to the external; and IO lines arranged to cross said memory cell array and to couple said bit line peripheral circuit and the IO means with each other.

Claim 30

A semiconductor memory device according to claim 25, wherein said IO lines are arranged perpendicular to said first bit lines.

Claim 31

A semiconductor memory device according to claim 26, wherein said IO lines are arranged parallel to said word lines.

Claim 32

A semiconductor memory device according to claim 25, wherein said IO lines are arranged parallel to said second bit lines.

Claim 33

A semiconductor memory device according to claim 29, wherein said IO lines and said second bit lines are formed by the same wiring layer.

Claim 34

A semiconductor memory device according to claim 26, wherein said memory cell array is divided into a plurality of blocks juxtaposed in a direction of said word lines; said semiconductor memory device further comprising word line selecting means for selecting one of said word lines in said divided memory cell array blocks, said word line selecting means includes a global row decoder provided commonly for said divided memory cell array blocks, local row decoders respectively provided for said memory cell array blocks, and a plurality of global row decoder output signal transmission lines arranged to pass over said respective memory cell array blocks for transmitting output signals from said global row decoder to said local row decoders.

Claim 35

A semiconductor memory device according to claim 31, wherein said global decoder output signal transmission lines are arranged parallel to said bit line signal IO lines.

Claim 36

A semiconductor memory device according to claim 32, wherein said global decoder output signal transmission lines and said second bit lines are formed by the same writing layer.

Claim 37

A semiconductor memory device according to claim 31, wherein said global decoder output signal transmission lines are arranged parallel to said IO lines.

Claim 38

A semiconductor memory device according to claim 34, wherein said global decoder output signal transmission lines and said IO lines are formed by the same wiring layer.

Claim 39

A semiconductor memory device according to claim 31, wherein said second bit lines and said IO lines are formed by the same wiring layer.

Claim 40

A semiconductor memory device according to claim 26, wherein said second bit lines are arranged parallel to each other.

Claim 41

A semiconductor memory device according to claim 37, wherein said second bit lines are arranged perpendicular to said first bit lines.

Claim 42

A semiconductor memory device according to claim 26, wherein said second bit lines are arranged parallel to said word lines.

Claim 43

A semiconductor memory device according to claim 26, wherein intervals between said second bit lines are larger than intervals between that of said first bit lines.

Claim 44

A semiconductor memory device according to claim 26, wherein said memory cells are static memory cells performing static storage of information.

Claim 45

A semiconductor memory device according to claim 26, wherein said memory cells are dynamic memory cells performing dynamic storage of information.

Claim 46

A semiconductor memory device comprising a memory cell array including a plurality of word lines, a plurality of first bit lines arranged to cross said word lines and a plurality of memory cells arranged at crossings of said word lines and said first bit lines; bit line peripheral circuit means arranged at least at one location transverse to the direction of said first bit lines; and second bit lines for connecting said first bit lines to said bit line peripheral circuit means, said second bit lines being arranged within said memory cell array and directly connected to said first bit lines so as to establish an interconnection node common to said second bit lines and corresponding first bit lines.

Claim 47

A semiconductor memory device comprising a memory cell array including a plurality of word lines, a plurality of first bit lines arranged to cross said word lines and a plurality of memory cells arranged at crossings of said word lines and said first bit lines; bit line peripheral circuit means arranged at least at one location transverse to the direction of said first bit lines; and second bit lines for connecting said first bit lines to said bit line peripheral circuit means, said second bit lines being arranged within said memory cell array and directly connected to said first bit lines so as to establish an interconnection node common to said second bit lines and corresponding first bit lines.

Claim 48

The device of claim 43 wherein said connecting means comprises a plurality of second bit lines arranged to cross said first bit lines, each second bit line being directly connected to corresponding one of said first bit lines within said memory cell array and having one end extended to an end portion of said memory cell array.

Claim 49

A semiconductor memory device comprising a memory cell array including a plurality of word lines, a plurality of first bit lines having a first pitch and being arranged to cross said word lines, and a plurality of memory cells arranged at crossings of said word lines and said first bit lines; bit line peripheral circuit means coupled to the first bit lines and including IO signal lines having a second pitch different from said first pitch; and means for establishing signal flow paths between said bit lines and said peripheral circuit IO signal lines, said establishing means being arranged within said memory cell array, wherein said signal flow paths establishing means comprises a plurality of second bit lines arranged to cross said first bit lines within said memory cell array, said second bit lines being directly connected to said first bit lines so as to establish an interconnection node common to said second and corresponding first bit lines.

Claim 50

A semiconductor memory device comprising a memory cell array including a plurality of word lines, a plurality of first bit lines having a first pitch and being arranged to cross said word lines, and a plurality of memory cells arranged at crossings of said word lines and said first bit lines; bit line peripheral circuit means coupled to the first bit lines and including IO signal lines having a second pitch different from said first pitch; and means for establishing signal flow paths between said bit lines and said peripheral circuit IO signal lines, said establishing means being arranged within said memory cell array, wherein said signal flow paths establishing means comprises a plurality of second bit lines arranged to cross said first bit lines within said memory cell array, said second bit lines being directly connected to said first bit lines so as to establish an interconnection node common to said second and corresponding first bit lines.

Claim 51

A semiconductor memory device comprising a memory cell array including a plurality of word lines, a plurality of bit lines arranged to cross said word lines, and a plurality of memory cells arranged at crossings of said word lines and said bit lines; bit lines peripheral circuit means arranged at least at one location transverse to the direction of said bit lines; and a signal flow path between said bit lines and said bit line peripheral circuits, said signal flow path being arranged within said memory cell array and directly connected to said bit line so as to establish an interconnection node common to said establishing means and corresponding bit lines.

Claim 52

A semiconductor memory device comprising a memory cell array including a plurality of word lines, a plurality of bit lines arranged to cross said word lines, and a plurality of memory cells arranged at crossings of said word lines and said bit lines; bit lines peripheral circuit means arranged at least at one location transverse to the direction of said bit lines; and a signal flow path between said bit lines and said bit line peripheral circuits, said signal flow path being arranged within said memory cell array and directly connected to said bit line so as to establish an interconnection node common to said establishing means and corresponding bit lines.

Claim 53

A semiconductor memory device comprising a memory cell array including a plurality of word lines, a plurality of first bit lines arranged to cross said word lines and a plurality of memory cells arranged at crossings of said word lines and said first bit lines; said device further comprising: a plurality of second bit lines arranged to cross said first bit lines and connected to corresponding said first bit lines, each having at least one end extended to an end of said memory cell array, said second bit lines being directly connected to said first bit lines so as to establish an interconnection node common to said second and corresponding first bit lines; a bit line peripheral circuit arranged at an end of said memory cell array and coupled to said second bit lines; IO means for inputting external data and/or a signal from and for outputting an internal signal and/or data to the external; and IO lines arranged to cross but not interact said memory cell array and to couple said bit line peripheral circuit and the IO means with each other.

Claim 54

A semiconductor memory device comprising a memory cell array including a plurality of word lines, a plurality of first bit lines arranged to cross said word lines and a plurality of memory cells arranged at crossings of said word lines and said first bit lines; said device further comprising: a plurality of second bit lines arranged to cross said first bit lines and connected to corresponding said first bit lines, each having at least one end extended to an end of said memory cell array, said second bit lines being directly connected to said first bit lines so as to establish an interconnection node common to said second and corresponding first bit lines; a bit line peripheral circuit arranged at an end of said memory cell array and coupled to said second bit lines; IO means for inputting external data and/or a signal from and for outputting an internal signal and/or data to the external; and IO lines arranged to cross but not interact said memory cell array and to couple said bit line peripheral circuit and the IO means with each other.

Claim 55

A semiconductor memory device, comprising: a memory cell array formed on a semiconductor substrate and having a plurality of memory cells arranged in a matrix with rows and columns, a region forming said memory cells arranged in a matrix with rows and columns, a region forming said memory cell array being substantially rectangular in shape; a plurality of word lines arranged in rows, each word line being connected to a plurality of memory cells arranged in the corresponding row, a plurality of bit lines arranged in columns, each bit line being connected to a plurality of memory cells arranged in the corresponding columns, at least a pair of IO lines arranged on the semiconductor substrate for connecting said bit line peripheral circuit means with the bit lines, said plurality of bit lines being formed by a bit line layer and said pair of IO lines being formed by an interconnection layer different from said bit line layer, row decoder means for selecting one of said plurality of word lines and arranged in parallel with first and third edges of said memory cell array parallel with column and formed on said semiconductor substrate outside said memory cell array, and bit line peripheral circuit means for receiving a signal on said bit lines and arranged in parallel with said first and third edges of said memory cell array and formed on said semiconductor substrate outside said memory cell array.

Claim 56

A semiconductor memory device, comprising: a memory cell array formed on a semiconductor substrate and having a plurality of memory cells arranged in a matrix with rows and columns, a region forming said memory cells arranged in a matrix with rows and columns, a region forming said memory cell array being substantially rectangular in shape; a plurality of word lines arranged in rows, each word line being connected to a plurality of memory cells arranged in the corresponding row, a plurality of bit lines arranged in columns, each bit line being connected to a plurality of memory cells arranged in the corresponding columns, at least a pair of IO lines arranged on the semiconductor substrate for connecting said bit line peripheral circuit means with the bit lines, said plurality of bit lines being formed by a bit line layer and said pair of IO lines being formed by an interconnection layer different from said bit line layer, row decoder means for selecting one of said plurality of word lines and arranged in parallel with first and third edges of said memory cell array parallel with column and formed on said semiconductor substrate outside said memory cell array, and bit line peripheral circuit means for receiving a signal on said bit lines and arranged in parallel with said first and third edges of said memory cell array and formed on said semiconductor substrate outside said memory cell array.

Claim 57

A semiconductor memory device, comprising: a memory cell array formed on a semiconductor substrate and having a plurality of memory cells arranged in a matrix with rows and columns, a region forming said memory cell array being substantially rectangular in shape; a plurality of word lines arranged in rows, each word line being connected to a plurality of memory cells arranged in the corresponding row, a plurality of bit lines arranged in columns, each bit line being connected to a plurality of memory cells arranged in the corresponding column, at least a pair of IO lines connected to said bit lines and arranged on said semiconductor substrate inside said memory cell array, said plurality of bit lines being formed by a bit line layer and said pair of IO lines being formed by an interconnection layer different from said bit line layer, row decoder means for selecting one of said plurality of word lines and formed on said semiconductor substrate outside a first edge of said memory cell array and arranged in parallel with said columns; first bit line peripheral circuit means formed on said semiconductor substrate outside a second edge of said memory cell array and arranged in parallel with said rows; second bit line peripheral circuit means formed on said semiconductor substrate outside a third edge of said memory cell array, connected to said IO lines and arranged in parallel with said columns; and third bit line peripheral circuit means formed on said semiconductor substrate outside a fourth edge of said memory cell array and arranged in parallel with said rows.

Claim 58

A semiconductor memory device, comprising: a memory cell array formed on a semiconductor substrate and having a plurality of memory cells arranged in a matrix with rows and columns, a region forming said memory cell array being substantially rectangular in shape; a plurality of word lines arranged in rows, each word line being connected to a plurality of memory cells arranged in the corresponding row, a plurality of bit lines arranged in columns, each bit line being connected to a plurality of memory cells arranged in the corresponding column, at least a pair of IO lines connected to said bit lines and arranged on said semiconductor substrate inside said memory cell array, said plurality of bit lines being formed by a bit line layer and said pair of IO lines being formed by an interconnection layer different from said bit line layer, row decoder means for selecting one of said plurality of word lines and formed on said semiconductor substrate outside a first edge of said memory cell array and arranged in parallel with said columns; first bit line peripheral circuit means formed on said semiconductor substrate outside a second edge of said memory cell array and arranged in parallel with said rows; second bit line peripheral circuit means formed on said semiconductor substrate outside a third edge of said memory cell array, connected to said IO lines and arranged in parallel with said columns; and third bit line peripheral circuit means formed on said semiconductor substrate outside a fourth edge of said memory cell array and arranged in parallel with said rows.

Claim 59

The device of claim 49, wherein said first bit line peripheral circuit includes a bit line load circuit, said second bit line peripheral circuit means having a write circuit for writing data to a memory cell in said memory cell array, and said third bit line peripheral circuit means having a read circuit for reading out the data stored in a memory cell of said memory cell array.

Claim 60

A semiconductor memory device according to claim 1, wherein said second bit lines are connected to the corresponding first bit lines within said memory cell array.

Claim 61

A semiconductor memory device according to claim 1, wherein at least one of said plurality of second bit lines is arranged between said word lines.

Claim 62

A semiconductor memory device according to claim 15, wherein at least one of said plurality of second bit lines is arranged between said word lines.

Claim 63

A semiconductor memory device according to claim 48, wherein said IO lines are directly connected to the bit lines so as to establish an interconnection node common to said IO lines and corresponding bit lines.

Claim 64

A semiconductor memory device according to claim 54, wherein said pair of IO lines is arranged within said memory cell array.

Claim 65

A semiconductor memory device according to claim 49, wherein said IO lines are directly connected to said bit lines so as to establish an interconnection node common to said IO lines and corresponding bit lines.