Multi-dimensional memory cell using resonant tunneling diodes

Claim 2

A memory cell for storing plural logical states comprising: first and m-second type devices that are selected to operate in a hysteretic condition; the first type device that is a loading means on the memory cell that enables the memory cells multiple operating points; the m-second type devices each having a folding voltage-current characteristic with N peaks where N≧1; wherein the first and second type devices are adapted to be connected in series across a power supply which is adjusted to produce a required number of stable logical operating states for the memory cell; and at least one access line that attaches to access memory data means to each node point of the series connected first and m-second type devices which are not at the power supply's potential or ground node point whereby the memory cell can enable the required number of stable logical operating states of the memory cell.

Claim 3

The memory cell as recited in claim 1 wherein the access memory data means allows for writing into the cell by parallel data signal processing at more than one node of the memory cell.

Claim 4

The memory cell as recited in claim 1 wherein the first type device and m second type devices are resonant tunneling diodes such that greater than (N+1) m stable logical operating states can be enabled and m≧2.

Claim 5

The memory cell as recited in claim 3 wherein the potential node of the device includes a means for connecting either a positive power supply or a negative power supply with respect to the memory cell's ground node reference thereby doubling the number of logical states.

Claim 6

The memory cell as recited in claim 1 wherein the loading means is a resistor that induces hysteresis in the second devices voltage-current folding characteristic such that up to (N+1) m stable logical operating states can be enabled.

Claim 7

The memory cell as recited in claim 5 wherein the potential node of the device includes a means for connecting either a positive power supply or a negative power supply with respect to the memory cells ground node reference thereby doubling the number of logical states.

Claim 8

The memory cell as recited in claim 1 wherein there is only one access line.

Claim 9

The memory cell as recited in claim 7 wherein the access memory data means for writing has only one defined type signal input.

Claim 10

The memory cell as recited in claim 8 wherein the signal input is of a single pulse type characteristic.

Claim 11

The memory cell as recited in claim 8 wherein the signal input is of a multi-step type characteristic.

Claim 12

The memory cell as recited in claim 7 wherein the potential node of the device includes a means for connecting either a positive power supply or a negative power supply with respect to the memory cells ground node reference thereby doubling the number of logical states.

Claim 13

The memory cell as recited in claim 1 wherein the loading device is a current source with a high internal impedance such that up to (N+1) m stable logical operating states can be enabled.

Claim 14

The memory cell as recited in claim 12 wherein the potential node of the device includes a means for connecting either a positive power supply or a negative power supply with respect to the memory cells ground node reference thereby doubling the number of logical states.

Claim 15

The memory cell as recited in claim 1 wherein the potential node of the device includes a means for connecting either a positive power supply or a negative power supply with respect to the memory cells ground node reference thereby doubling the number of logical states.

Claim 16

A memory system for storing plural logic states comprising: an array of memory cells with address means for addressing the memory cells; a reading means for reading the memory cells; a writing means for writing onto the memory cell wherein each memory cell includes a first and m-second type devices that are selected to operate in a hysteretic condition; the first type device is a loading means on the memory cell that enables the memory cell's multiple operating points; the m-second type devices each having a folding voltage-current characteristic with N peaks where N≧1; wherein the first and m-second type devices are adapted to be connected in series across a power supply which is adjusted to produce a required number of stable logical operating states for the memory cell; and at least one access line that attaches the access memory data means to each node point of the series connected first and second devices which are not at the power supply's potential or ground node point whereby the memory cell can enable the required number of stable logical operating states of the memory cell.

Claim 17

A memory system for storing plural logic states comprising: an array of memory cells with address means for addressing the memory cells; a reading means for reading the memory cells; a writing means for writing onto the memory cell wherein each memory cell includes a first and m-second type devices that are selected to operate in a hysteretic condition; the first type device is a loading means on the memory cell that enables the memory cell's multiple operating points; the m-second type devices each having a folding voltage-current characteristic with N peaks where N≧1; wherein the first and m-second type devices are adapted to be connected in series across a power supply which is adjusted to produce a required number of stable logical operating states for the memory cell; and at least one access line that attaches the access memory data means to each node point of the series connected first and second devices which are not at the power supply's potential or ground node point whereby the memory cell can enable the required number of stable logical operating states of the memory cell.

Claim 18

The memory system as recited in claim 15 wherein each memory cell's access memory data means allows for writing into the cell by parallel data signal processing at more than one node of the memory cell.

Claim 19

The memory system as recited in claim 15 wherein each memory cell's first type device and m-second type devices are resonant tunneling diodes such that greater than (N+1) m stable logical operating states can be enabled and m≧2.

Claim 20

The memory system as recited in claim 17 wherein each memory cell's power supply's potential node of each cell includes a means for connecting either a positive power supply or a negative power supply with respect to the memory cell's ground node reference thereby doubling the number or required operating states.

Claim 21

The memory system as recited in claim 15 wherein each memory cell's loading means is a resistor that induces hysteresis in the second devices voltage-current folding characteristic such that up to (N+1) m stable logical operating states can be enabled.

Claim 22

The memory system as recited in claim 19 wherein each memory cell's power supply's potential node of each cell includes a means for connecting either a positive power supply or a negative power supply with respect to the memory cell's ground node reference thereby doubling the number or required operating states.

Claim 23

The memory system as recited in claim 15 wherein each memory cell has only one access line.

Claim 24

The memory system as recited in claim 21 wherein the access memory data means for writing has only one defined type signal input.

Claim 25

The memory system as recited in claim 22 wherein the signal input is of a single pulse type characteristic.

Claim 26

The memory system as recited in claim 22 wherein the signal input is of a multi-step type characteristic.

Claim 27

The memory system as recited in claim 21 wherein each memory cell's power supply's potential node of each cell includes a means for connecting either a positive power supply or a negative power supply with respect to the memory cell's ground node reference thereby doubling the number or required operating states.

Claim 28

The memory system as recited in claim 15 wherein each memory cell's loading device is a current source with a high internal impedance such that up to (N+1) m stable logical operating states can be enabled.

Claim 29

The memory system as recited in claim 26 wherein each memory cell's power supply's potential node of each cell includes a means for connecting either a positive power supply or a negative power supply with respect to the memory cell's ground node reference thereby doubling the number or required operating states.

Claim 30

The memory system as recited in claim 15 wherein each memory cell's power supply's potential node of each cell includes a means for connecting either a positive power supply or a negative power supply with respect to the memory cell's ground node reference thereby doubling the number of logical states.