Majority logic circuit

Claim 2

A logic circuit having first and second power source terminals and three input terminals for receiving three respective input signals, each of the input signals having, selectively, either a high level or a low level, and an output terminal, comprising: a transistor having a first electrode connected to the first power source terminal, a second electrode and a control electrode connected to the three input terminals; a diode, having N-type negative differential resistance, connected between the second electrode of the transistor and the second power source terminal; the output terminal being connected to the first electrode of the transistor for deriving an output signal therefrom; and means for setting the load lines of the transistor to a first operating point wherein, for each of a first condition in which all of the three input signals are at a low level and a second condition in which two of the input signals are at a high level and a third of the input signals is at a low level, the current conducted by the transistor is at a first level, and to a second operating point wherein, for each of a third condition in which only one of the input signals is at the high level and the remaining two input signals are at the low level and a fourth condition in which all of the three input signals are at the high level, the current conducted by the transistor is at a second level, greater than the first level.

Claim 3

A logic circuit as recited in claim 1, further comprising: a resistor having a first end connected at a node to the first electrode of the transistor and a second end connected to the first power supply terminal; and the output terminal is connected to the node.

Claim 4

A logic circuit as recited in claim 1, wherein said transistor comprises a bipolar transistor.

Claim 5

A logic circuit as recited in claim 1, wherein said transistor comprises a field effect transistor.

Claim 6

A logic circuit as recited in claim 1, wherein said transistor comprises a static induction transistor.

Claim 7

A logic circuit as recited in claim 1, wherein said N-type diode comprises a resonance tunnel diode.

Claim 8

A logic circuit as recited in claim 1, wherein said N-type diode comprises an Esaki diode.

Claim 9

A logic circuit as recited in claim 1, wherein said N-type diode comprises a real space transition type differential characteristic resistance element.

Claim 10

A logic circuit having first and second power source terminals and three input terminals for receiving three respective input signals, each of the input signals having, selectively, either a high or a low level, and an output terminal, comprising: a transistor having a first electrode connected to the first power source terminal, a second electrode and a control electrode connected to the three input terminals; a diode, having N-type negative differential resistance, connected between the second electrode of the transistor and the second power source terminal; and means connecting the output terminal to the second electrode of the transistor for deriving a voltage therefrom and producing a corresponding output voltage at the output terminal, the output voltage having a first voltage level when the number of the respective input signals, received by the three input terminals, having the high level is zero or one and the output voltage having a second voltage level, higher than the first voltage level, when the number of the respective input signals, received by the three input terminals, having the high level is two or three.

Claim 11

A logic circuit having first and second power source terminals and three input terminals for receiving three respective input signals, each of the input signals having, selectively, either a high or a low level, and an output terminal, comprising: a transistor having a first electrode connected to the first power source terminal, a second electrode and a control electrode connected to the three input terminals; a diode, having N-type negative differential resistance, connected between the second electrode of the transistor and the second power source terminal; and means connecting the output terminal to the second electrode of the transistor for deriving a voltage therefrom and producing a corresponding output voltage at the output terminal, the output voltage having a first voltage level when the number of the respective input signals, received by the three input terminals, having the high level is zero or one and the output voltage having a second voltage level, higher than the first voltage level, when the number of the respective input signals, received by the three input terminals, having the high level is two or three.

Claim 12

A logic circuit as recited in claim 9, wherein: the diode has a current-versus-voltage characteristic having a peak in a first voltage range and a valley in a second voltage range higher than the first voltage range; and the connecting means comprises a discrimination circuit which connects the output terminal to the second electrode of the transistor, the discrimination circuit establishing a discriminating voltage having a voltage level intermediate the first and second voltage ranges, and discriminating the voltage derived from the second electrode of the transistor relatively to the discriminating voltage and producing the output voltage, correspondingly and selectively of the first and second voltage levels.

Claim 13

A logic circuit as recited in claim 9, wherein said transistor comprises a bipolar transistor.

Claim 14

A logic circuit as recited in claim 9, wherein said transistor comprises a field effect transistor.

Claim 15

A logic circuit as recited in claim 9, wherein said transistor comprises a static induction transistor.

Claim 16

A logic circuit as recited in claim 9, wherein said N-type diode comprises a resonance tunnel diode.

Claim 17

A logic circuit as recited in claim 9, wherein said N-type diode comprises an Esaki diode.

Claim 18

A logic circuit as recited in claim 9, wherein said N-type diode comprises a real space transition type differential characteristic resistance element.

Claim 19

A logic circuit having first and second power source terminals and three input terminals for receiving three respective input signals, each of the input signals having, selectively, either a high level or a low level, and first and second output terminals, comprising: a transistor having a first electrode connected to the first power source terminals, a second electrode and a control electrode connected to the three input terminals; a diode, having N-type negative differential resistance, connected between the second electrode of the transistor and the second power source terminal; the first output terminal being connected to the first electrode of the transistor for deriving an output signal therefrom; means for setting the load lines of the transistor to a first operating point wherein, for each of a first condition in which all of the three input signals are at a low level and a second condition in which two of the input signals are at a high level and a third of the input signals is at a low level, the current conducted by the transistor is at a first level, and to a second operating point wherein, for each of a third condition in which only one of the input signals is at the high level and the remaining two input signals are at the low level and a fourth condition in which all of the three input signals are at the high level, the current conducted by the transistor is at a second level, greater than the first level; and means connecting the second output terminal to the second electrode of the transistor for deriving and producing a corresponding output voltage at the output terminal, the output voltage having a first voltage level when the number of the respective input signals, received by the three input terminals, having the high level is zero or one and the output voltage having a second voltage level, higher than the first voltage level, when the number of the respective input signals, received by the three input terminals, having the high level is two or three.

Claim 20

A logic circuit having first and second power source terminals and three input terminals for receiving three respective input signals, each of the input signals having, selectively, either a high level or a low level, and first and second output terminals, comprising: a transistor having a first electrode connected to the first power source terminals, a second electrode and a control electrode connected to the three input terminals; a diode, having N-type negative differential resistance, connected between the second electrode of the transistor and the second power source terminal; the first output terminal being connected to the first electrode of the transistor for deriving an output signal therefrom; means for setting the load lines of the transistor to a first operating point wherein, for each of a first condition in which all of the three input signals are at a low level and a second condition in which two of the input signals are at a high level and a third of the input signals is at a low level, the current conducted by the transistor is at a first level, and to a second operating point wherein, for each of a third condition in which only one of the input signals is at the high level and the remaining two input signals are at the low level and a fourth condition in which all of the three input signals are at the high level, the current conducted by the transistor is at a second level, greater than the first level; and means connecting the second output terminal to the second electrode of the transistor for deriving and producing a corresponding output voltage at the output terminal, the output voltage having a first voltage level when the number of the respective input signals, received by the three input terminals, having the high level is zero or one and the output voltage having a second voltage level, higher than the first voltage level, when the number of the respective input signals, received by the three input terminals, having the high level is two or three.

Claim 21

A logic circuit as recited in claim 17, wherein: the diode has a current-versus-voltage characteristic having a peak in a first voltage range and a valley in a second voltage range higher than the first voltage range; and the connecting means comprises a discrimination circuit which connects the output terminal to the second electrode of the transistor, the discrimination circuit establishing a discriminating voltage having a voltage level intermediate the first and second voltage ranges, and discriminating the voltage derived from the second electrode of the transistor relatively to the discriminating voltage and producing the output voltage, correspondingly and selectively of the first and second voltage levels.

Claim 22

A logic circuit as recited in claim 17, wherein said transistor comprises a bipolar transistor.

Claim 23

A logic circuit as recited in claim 17, wherein said transistor comprises a field effect transistor.

Claim 24

A logic circuit as recited in claim 17, wherein said transistor comprises a static induction transistor.

Claim 25

A logic circuit as recited in claim 17, wherein said N-type diode comprises a resonance tunnel diode.

Claim 26

A logic circuit as recited in claim 17, wherein said N-type diode comprises an Esaki diode.

Claim 27

A logic circuit as recited in claim 17, wherein said N-type diode comprises a real space transition type differential characteristic resistance element.

Claim 28

A logic circuit having high and low potential power supply terminals, three input terminals for receiving three respective input signals, each of the input signals having, selectively, either a high voltage level or a low voltage level, and an output terminal, comprising: a transistor having first and second electrodes and a control electrode; first, second and third resistors respectively connecting the control electrode of the transistor to the three input terminals; a fourth resistor connecting the first electrode of the transistor to the high potential power supply terminal; a fifth resistor connecting the control electrode of the transistor to the low potential power supply terminal; a diode, having N-type negative differential resistance, connecting the second electrode of the transistor to the low potential power supply terminal; the output terminal being connected to the connection of the second electrode and the diode; and the voltage-versus-current characteristics of the transistor and the diode and the values of the resistors being selected, relatively to the voltage levels of the first, second and third input signals and the values of the high and low potential power supplies, so as to set the load lines of the transistor at selected, different values respectively corresponding to, and in response to, the respective, high or low voltage levels of the three input signals respectively received at the three input terminals and supplied through the respective first, second and third resistors to the control electrode of the transistor.

Claim 29

A logic circuit having high and low potential power supply terminals, three input terminals for receiving three respective input signals, each of the input signals having, selectively, either a high voltage level or a low voltage level, and an output terminal, comprising: a transistor having first and second electrodes and a control electrode; first, second and third resistors respectively connecting the control electrode of the transistor to the three input terminals; a fourth resistor connecting the first electrode of the transistor to the high potential power supply terminal; a fifth resistor connecting the control electrode of the transistor to the low potential power supply terminal; a diode, having N-type negative differential resistance, connecting the second electrode of the transistor to the low potential power supply terminal; the output terminal being connected to the connection of the second electrode and the diode; and the voltage-versus-current characteristics of the transistor and the diode and the values of the resistors being selected, relatively to the voltage levels of the first, second and third input signals and the values of the high and low potential power supplies, so as to set the load lines of the transistor at selected, different values respectively corresponding to, and in response to, the respective, high or low voltage levels of the three input signals respectively received at the three input terminals and supplied through the respective first, second and third resistors to the control electrode of the transistor.

Claim 30

A logic circuit having high and low potential power supply terminals, three input terminals for receiving three respective input signals, each of the input signals having, selectively, either a high voltage level or a low voltage level, and an output terminal, comprising: a first transistor having first and second electrodes and a control electrode; first, second and third resistors respectively connecting the control electrode of the first transistor to the three input terminals; a fourth resistor connecting the first electrode of the first transistor to the high potential power supply terminal; a fifth resistor connecting the control electrode of the first transistor to the low potential power supply terminal; a diode, having N-type negative differential resistance, connecting the second electrode of the first transistor to the low potential power supply terminal; the output terminal being connected to the connection of the second electrode and the diode; a second transistor having a control electrode connected to the second electrode of the first transistor and having first and second electrodes, the second electrode being connected to the low potential power supply terminal; a sixth resistor connecting the first electrode of the second transistor to the high potential power supply terminal; the output terminal being connected to the connection of the sixth resistor and the first electrode of the second transistor; and the voltage-versus-current characteristics of the first transistor and the diode and the values of the resistors being selected, relatively to the voltage levels of the first second and third input signals and the values of the high and low potential power supplies, so as to set the load lines of the first transistor at selected, different values respectively corresponding to, and in response to, the respective, high or low voltage levels of the three input signals respectively received at the three input terminals and supplied through the respective first, second and third resistors to the control electrode of the first transistor and so as to set a voltage threshold value of the second transistor intermediate the corresponding voltage values of the selected, different load lines of the first transistor.

Claim 31

A logic circuit having high and low potential power supply terminals, three input terminals for receiving three respective input signals, each of the input signals having, selectively, either a high voltage level or a low voltage level, and an output terminal, comprising: a first transistor having first and second electrodes and a control electrode; first, second and third resistors respectively connecting the control electrode of the first transistor to the three input terminals; a fourth resistor connecting the first electrode of the first transistor to the high potential power supply terminal; a fifth resistor connecting the control electrode of the first transistor to the low potential power supply terminal; a diode, having N-type negative differential resistance, connecting the second electrode of the first transistor to the low potential power supply terminal; the output terminal being connected to the connection of the second electrode and the diode; a second transistor having a control electrode connected to the second electrode of the first transistor and having first and second electrodes, the second electrode being connected to the low potential power supply terminal; a sixth resistor connecting the first electrode of the second transistor to the high potential power supply terminal; the output terminal being connected to the connection of the sixth resistor and the first electrode of the second transistor; and the voltage-versus-current characteristics of the first transistor and the diode and the values of the resistors being selected, relatively to the voltage levels of the first second and third input signals and the values of the high and low potential power supplies, so as to set the load lines of the first transistor at selected, different values respectively corresponding to, and in response to, the respective, high or low voltage levels of the three input signals respectively received at the three input terminals and supplied through the respective first, second and third resistors to the control electrode of the first transistor and so as to set a voltage threshold value of the second transistor intermediate the corresponding voltage values of the selected, different load lines of the first transistor.