US5284786A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a split floating gate EEPROM cell
Assignee: National Semiconductor Corp
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Filing: 1992-08-14
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Granted: 1994-02-08
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Expires: 2012-08-14
Abstract
Abstract A split floating gate EEPROM memory cell formed in a P-type silicon substrate includes source and drain buried n+ diffusion regions formed in the silicon substrate to define a substrate channel region therebetween. A layer of floating gate oxide about 400Å thick is formed over the source and drain regions and over the channel region. The floating gate oxide includes a region of thin tunnel oxide about 80-100Å thick formed therein over the drain region. A floating gate is formed on the floating gate oxide to extend over the channel region and includes a portion that extends over the tunnel oxide. The floating gate comprises a first layer of polysilicon about 300-600Å thick, a silicon dioxide layer about 20-50Å thick formed on the first layer of polysilicon, and a second layer of polysilicon about 2000Å thick formed on the silicon dioxide layer. A layer of ONO is formed on the floating gate and a polysilicon control gate is formed on the layer of ONO.
Inventors
- 👤 Rakesh B. Sethi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 04:32
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10B; H10B69/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D30/6891; H10D30/6892
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
208 words
A method of forming a split floating gate memory cell in a semiconductor substrate having a first conductivity type, the method comprising: (a) forming source and drain buried diffusion regions having a second conductivity type opposite the first conductivity type in the semiconductor substrate, the source and drain diffusion regions being spaced apart to define a substrate channel region therebetween; (b) forming a layer of floating gate dielectric material over the source and drain regions and the channel region, the floating gate dielectric material including a region of tunnel dielectric formed therein over the drain region such that the thickness of the tunnel dielectric is less than the thickness of the floating gate dielectric material; (c) forming a floating gate on the floating gate dielectric material to extend over the channel region and including a portion that extends over the tunnel dielectric, the floating gate comprising a layer of first conductive material, a layer of first dielectric material formed on the layer of first conductive material, and a layer of second conductive formed on the layer of first dielectric material; (d) forming a layer of second dielectric material on the floating gate; and (e) forming a layer of third conductive material on the layer of second dielectric material.
Claim 2
Independent Claim
208 words
A method of forming a split floating gate memory cell in a semiconductor substrate having a first conductivity type, the method comprising: (a) forming source and drain buried diffusion regions having a second conductivity type opposite the first conductivity type in the semiconductor substrate, the source and drain diffusion regions being spaced apart to define a substrate channel region therebetween; (b) forming a layer of floating gate dielectric material over the source and drain regions and the channel region, the floating gate dielectric material including a region of tunnel dielectric formed therein over the drain region such that the thickness of the tunnel dielectric is less than the thickness of the floating gate dielectric material; (c) forming a floating gate on the floating gate dielectric material to extend over the channel region and including a portion that extends over the tunnel dielectric, the floating gate comprising a layer of first conductive material, a layer of first dielectric material formed on the layer of first conductive material, and a layer of second conductive formed on the layer of first dielectric material; (d) forming a layer of second dielectric material on the floating gate; and (e) forming a layer of third conductive material on the layer of second dielectric material.
Claim 3
Dependent Claim
24 words
A method as in claim 1 wherein the semiconductor substrate is P-type silicon and the source and drain regions are buried n+ diffusion regions.
Claim 4
Dependent Claim
28 words
A method as in claim 2 wherein the floating gate dielectric material is silicon dioxide about 400Å thick and the tunnel dielectric is silicon dioxide about 80-100Å thick.
Claim 5
Dependent Claim
36 words
A method as in claim 2 wherein the first conductive material is polysilicon about 300-600Å thick, the first dielectric material is silicon dioxide about 20-50Å thick, and the second conductive material is polysilicon about 2000Å thick.
Claim 6
Dependent Claim
20 words
A method as in claim 2 wherein the second dielectric material is a sandwich of oxide/nitride/oxide (ONO) about 200-250Å thick.
Claim 7
Dependent Claim
16 words
A method as in claim 2 wherein the third conductive material is polysilicon about 4000Å thick.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-07 | 1997-08-09 | 1998-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-07 | 2001-08-09 | 2002-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-07 | 2005-08-09 | 2006-02-08 | $7700.00 | Window Closed / Lapsed |