Timing coinciding circuit simultaneously supplying two power supply voltages applied in different timing

Claim 2

A semiconductor integrated circuit device including first and second internal circuits, respectively energized by externally applied at least first and second power supply voltages, wherein said second internal circuit has a tendency to consume much current in response to an unstable output signal provided from said first internal circuit when said second power supply voltage only is applied, comprising: timing coinciding means responsive to the supply-timing of one of the first and second voltages for making the other supply-timing of the first and second power supply voltages coincide with said one, wherein said first and second power supply voltages are applied to said first and second internal circuits, respectively, through said timing coinciding means.

Claim 3

The semiconductor integrated circuit device according to claim 1, wherein said timing coinciding means comprises means responsive to supply-start timing of delayed one of said first and second power supply voltages for delaying the other preceding one of said first and second power supply voltages.

Claim 4

The semiconductor integrated circuit device according to claim 1, wherein said timing coinciding means comprises means responsive to supply-end timing of preceding one of said first and second power supply voltages for making earlier supply-end timing of the other delayed one of said first and second power supply voltages.

Claim 5

The semiconductor integrated circuit device according to claim 1, wherein said second internal circuit comprises driving circuit means for driving an externally provided load in response to an output-signal provided from said first internal circuit, said driving circuit means having a tendency to consume much current in response to the unstable output signal provided from said first internal circuit when said second power supply voltage only is applied.

Claim 6

The semiconductor integrated circuit device according to claim 1, wherein said timing coinciding means includes; a first power supply voltage input terminal for receiving said first power supply voltage, a second power supply voltage input terminal for receiving said second power supply voltage, first switching means connected between said first power supply input terminal and first internal circuit being operated in response to the voltage applied to said second power supply voltage input terminal, and second switching means connected between said second power supply voltage input terminal and second internal circuit being operated in response to the voltage applied to said first power supply voltage input terminal.

Claim 7

The semiconductor integrated circuit device according to claim 5, wherein said first switching means comprises a first transmission gate connected between said first power supply voltage input terminal and first internal circuit, and being turned on in response to a high level voltage applied to said second power supply voltage input terminal; and said second switching means comprises second transmission gate connected between said second power supply voltage terminal and second internal circuit, and being turned on in response to a high level voltage applied to said first power supply voltage input terminal.

Claim 8

The semiconductor integrated circuit device according to claim 4, wherein said driving circuit means comprises a plurality of switching elements connected in series between said second power supply voltage and the ground and being operated in response to the output signal provided from said first internal circuit; and said load is connected to a common connection node of said plurality of switching elements.

Claim 9

A semiconductor memory device energized by externally applied at least first and second power supply voltages, comprising: data storing means supplied with said first power supply voltage for storing a data signal; data read out means supplied with said first power supply voltage for reading out the data signal stored in said data storing means in response to an externally applied read out control signal; data output terminals for providing the data signal read out from said data read out means; driving circuit means supplied with said second power supply voltage for driving said data output terminals in response to the data signal read out by said data reading out means, said driving circuit means has a tendency to consume much current in response to an unstable output signal provided from said data read out means when said second power supply voltage only is applied; and timing coinciding means responsive to the supply-timing of one of the first and second voltages received for making the other supply-timing of the first and second power supply voltages coincide with said one, said first and second power supply voltages being respectively applied to said data storing means and data read out means, and said driving circuit means through said timing coinciding means.

Claim 10

A semiconductor memory device energized by externally applied at least first and second power supply voltages, comprising: data storing means supplied with said first power supply voltage for storing a data signal; data read out means supplied with said first power supply voltage for reading out the data signal stored in said data storing means in response to an externally applied read out control signal; data output terminals for providing the data signal read out from said data read out means; driving circuit means supplied with said second power supply voltage for driving said data output terminals in response to the data signal read out by said data reading out means, said driving circuit means has a tendency to consume much current in response to an unstable output signal provided from said data read out means when said second power supply voltage only is applied; and timing coinciding means responsive to the supply-timing of one of the first and second voltages received for making the other supply-timing of the first and second power supply voltages coincide with said one, said first and second power supply voltages being respectively applied to said data storing means and data read out means, and said driving circuit means through said timing coinciding means.

Claim 11

The semiconductor memory device according to claim 8, wherein said data storing means comprises a memory cell array including memory cells for storing data signals; said externally applied read out control signal comprises an externally applied address signal for addressing one of the memory cells in said memory cell array, said data read out means comprises memory cell designating means for designating one of the memory cells in said memory cell array in response to said address signal; sense amplifier means for amplifying a data signal stored in one of the memory cells designated by said memory cell designating means; output main amplifier circuit means for amplifying a data signal amplified by said sense amplifier means, said first power supply voltage being applied to said memory cell designating means, sense amplifier means, and output main amplifier circuit means.

Claim 12

The semiconductor memory device according to claim 9, wherein said memory cell designating means comprises decoder means for designating a row and a column in the memory cell array in response to said externally applied address signal.

Claim 13

The semiconductor memory device according to claim 8, wherein said semiconductor memory device has a multi-bits configuration for simultaneously handling n-bits of data signals.

Claim 14

The semiconductor memory device according to claim 8, wherein said semiconductor memory device comprises a dynamic random access memory device.