Memory-resource-driven arbitration

Claim 2

In a computer system, a method for improving bus utilization, the method comprising the steps of: (a) storing a memory address identification into an address storage when a memory transaction is initiated; (b) removing said memory address identification from said address storage when said memory transaction is completed; (c) checking the contents of said address storage before initiating a subsequent memory transaction to determine if a target memory address is busy; (d) initiating said subsequent memory transaction only if said target memory address is not busy; and (e) repeating steps (a) and (b) if said subsequent memory transaction is initiated.

Claim 3

A method as in claim 1 wherein step (a) further comprises the steps of: (a1) dividing a target memory into a plurality of blocks; (a2) interleaving said blocks; and (a3) computing a block identification from said target memory address so that for each block in said plurality of blocks, all target memory addresses within a block correspond to one unique block identification.

Claim 4

A method as in claim 2 further comprising the steps of: (a4) initiating said memory transaction during an address control state; (a5) setting an address valid bit to logical 1 if said memory transaction is initiated; (a6) setting said address valid bit to logical 0 if said address control state transpires without initiating said memory transaction; (a7) assigning said block identification and said address valid bit to said memory address identification each time said memory transaction is initiated; (a8) assigning an arbitrary block identification and said address valid bit to said memory address identification if said address control state transpires without initiating said memory transaction; and (a9) inserting said memory address identification into a queue within each master device in a plurality of master devices each time said address control state transpires.

Claim 5

A method as in claim 2 further comprising the steps of: (a4) initiating said memory transaction during an address control state; (a5) assigning said block identification to said memory address identification if said memory transaction is initiated; (a6) assigning an unused block identification to said memory address identification if said address control state transpires without initiating said memory transaction; and, (a7) inserting said memory address identification into a queue within each master device in a plurality of master devices each time said address control state transpires.

Claim 7

In a computer system having a plurality of master devices, a bus, and memory, an apparatus for improving utilization of said bus, said apparatus comprising: storage means for storing a memory address identification when a memory transaction is initiated; removal means for removing said memory address identification from said storage means when said memory transaction is complete; detection means for detecting whether a target memory address identification is stored in said storage means, thereby determining whether an area of memory corresponding to said target memory address identification is busy; and, inhibiting means for inhibiting initiation of said memory transaction if said target memory address identification is stored in said storage means.

Claim 8

In a computer system having a plurality of master devices, a bus, and memory, an apparatus for improving utilization of said bus, said apparatus comprising: storage means for storing a memory address identification when a memory transaction is initiated; removal means for removing said memory address identification from said storage means when said memory transaction is complete; detection means for detecting whether a target memory address identification is stored in said storage means, thereby determining whether an area of memory corresponding to said target memory address identification is busy; and, inhibiting means for inhibiting initiation of said memory transaction if said target memory address identification is stored in said storage means.

Claim 9

An apparatus as in claim 6 wherein said identification means further comprises: block means for dividing said memory into a plurality of blocks; block identification means for computing a plurality of block identifications, wherein each block in said plurality of blocks has a one-to-one correspondence to one block identification in said plurality of block identifications and wherein a plurality of memory addresses may correspond to one block identification; an address valid bit, wherein said address valid bit is set to logical 1 if said memory transaction is initiated during said address control state and said address valid bit is set to logical 0 if said memory transaction is not initiated during said address control state; said memory address identification comprising said block identification and said address valid bit if said memory transaction is initiated during said address control state; and said memory address identification comprising an arbitrary block identification and said address bit if a memory transaction is not initiated during said address control state.

Claim 10

An apparatus as in claim 6 wherein said identification means further comprises: block means for dividing said memory into a plurality of blocks; block identification means for computing a plurality of block identifications, wherein each block in said plurality of blocks has a one-to-one correspondence to one block identification in said plurality of block identifications and wherein a plurality of memory addresses may be assigned to one block identification; said memory address identification comprising said corresponding block address if said memory transaction is initiated during said address control state; and said memory address identification comprising an unused block identification if said memory transaction is not initiated during said address control state.

Claim 12

An apparatus as in claim 9 wherein said comparison means is a digital comparator.