US5291489A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interprocessor switching network
Assignee: Alcatel Lucent Holdings Inc
•
Filing: 1992-02-12
•
Granted: 1994-03-01
•
Expires: 2012-02-12
Abstract
Abstract A message transport network (10) is provided for high speed switching between processing elements (72, 80). Clusters of low speed processing elements (72) may be connected to the message transport network (10) through a transport node controller (78). The transport node controller (78) and the high speed processors (80) are connected to the gateways (82). A pair of gateways (82) may be connected through a transport interchange node (106) to allow communication between processors (72, 80) associated with the gateways (82). A transport interchange supervisor (98) maintains a record of the status of each gateway (82) and generates commands to form connection between gateways (82) in the transport interchange node (106). A maintenance controller (102) and system maintenance processor (76) oversee the validity of the data being passed through the system on paths independent of the data transfer paths. The message transport network (10) may be used in variety of applications, such as a telephony switch (11), a signaling transfer point system (21) or a fault tolerant minicomputer (49).
Inventors
- 👤 James D. Morgan
- 👤 Allen R. Adams, Jr.
- 👤 Robert E. Nimon
- 👤 Edgar L. Read
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:41
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0407; G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/16; H04L; H04L49/00; H04L49/55; H04L49/552; H04L49/555; H04L49/557; G06F11/22; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L2012/5625; H04L2012/5627; H04L49/40
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
117 words
Communication circuitry for a plurality of processors, comprising: first transfer circuitry responsive to program code and capable of transferring interprocessor communications between a predetermined first set of said plurality of processors, second transfer circuitry responsive to program code and capable of transferring interprocessor communications between said predetermined first set of said plurality of processors and at least a second set of said plurality of processors and operable to allow simultaneous and distinct communications among said plurality of processors, and control circuit for sensing changes in at least one of said plurality of processors and for responding to said sensed changes by dynamically modifying said program code for at least one of said first and second transfer circuitry.
Claim 2
Dependent Claim
117 words
Communication circuitry for a plurality of processors, comprising: first transfer circuitry responsive to program code and capable of transferring interprocessor communications between a predetermined first set of said plurality of processors, second transfer circuitry responsive to program code and capable of transferring interprocessor communications between said predetermined first set of said plurality of processors and at least a second set of said plurality of processors and operable to allow simultaneous and distinct communications among said plurality of processors, and control circuit for sensing changes in at least one of said plurality of processors and for responding to said sensed changes by dynamically modifying said program code for at least one of said first and second transfer circuitry.
Claim 3
Dependent Claim
21 words
The circuitry of claim 1, wherein said first transfer circuitry includes an associated first instruction memory for containing said program code.
Claim 4
Dependent Claim
16 words
The circuitry of claim 2, wherein said first instruction memory is connected to said control circuitry.
Claim 5
Dependent Claim
29 words
The circuitry of claim 3, wherein said first instruction memory is divided into a plurality of sections corresponding to processors in said first set of said plurality of processors.
Claim 6
Dependent Claim
36 words
The circuitry of claim 4, wherein said control circuitry is operable to modify a section of said plurality of sections of said first instruction memory associated with one of said processors to initiate a communication therefrom.
Claim 7
Dependent Claim
36 words
The circuitry of claim 4, wherein said control circuitry is operable to modify a section of said plurality of sections of said first instruction memory associated with one of said processors to enable a communication therewith.
Claim 8
Dependent Claim
21 words
The circuitry of claim 1, wherein said second transfer circuitry includes an associated second instruction memory for containing said program code.
Claim 9
Dependent Claim
16 words
The circuitry of claim 7, wherein said second instruction memory is connected to said control circuitry.
Claim 10
Dependent Claim
20 words
The circuitry of claim 7, wherein said second instruction memory has predefined sections associated with predetermined ones of said processors.
Claim 11
Dependent Claim
39 words
The circuitry of claim 9, wherein said control circuitry is operable to modify one or more of said predefined sections of said second instruction memory to indicate that the respective associated processors are not ready to receive a communication.
Claim 12
Dependent Claim
29 words
The circuitry of claim 1, further comprising: a memory interconnected with said first transfer circuitry and said second transfer circuitry for temporarily storing communications between said plurality of processors.
Claim 13
Dependent Claim
33 words
The circuitry of claim 11, further comprising: circuitry interconnected with said control circuitry for monitoring the performance and operating status of said first and second transfer circuitry, said control circuitry, and said memory.
Claim 14
Dependent Claim
47 words
The circuitry of claim 11, wherein said control circuitry is operable to provide said first transfer circuitry a starting address in said memory at which a communication from a first one of said processors in said predetermined first set of said plurality of processors may be stored.
Claim 15
Dependent Claim
38 words
The circuitry of claim 13, wherein said control circuitry is further operable to provide said first transfer circuitry with a number indicating the number of bytes of data in said communication from said first one of said processors.
Claim 16
Dependent Claim
50 words
The circuitry of claim 14, wherein said control circuitry is operable to provide a starting address and byte count information to said second transfer circuitry for a communication in said memory to be transferred to one of said processors in said at least second set of said plurality of processors.
Claim 17
Dependent Claim
25 words
The circuitry of claim 11, wherein said predetermined first set of said plurality of processors and said first transfer circuitry are interconnected by a bus.
Claim 18
Dependent Claim
22 words
The circuitry of claim 16, wherein said first transfer circuitry includes direct memory access circuitry interconnected between said bus and said memory.
Claim 19
Dependent Claim
50 words
The circuitry of claim 16, wherein said first transfer circuitry includes circuitry for detecting status information generated by a first processor in said predetermined first set of said plurality of processors to initiate a communication to a second processor in said at least second set of said plurality of processors.
Claim 20
Dependent Claim
19 words
The circuitry of claim 11, wherein said second transfer circuitry includes direct memory access circuitry connected to said memory.
Claim 21
Dependent Claim
41 words
The circuitry of claim 1, further comprising: a first signal line connected to said control circuitry for use during communications between said predetermined first set of said plurality of processors and said at least second set of said plurality of processors.
Claim 22
Dependent Claim
25 words
The circuitry of claim 1, wherein said predetermined first set of said plurality of processors and said first transfer circuitry are interconnected by a bus.
Claim 23
Dependent Claim
49 words
The circuitry of claim 1, wherein said first transfer circuitry includes circuitry for detecting status information generated by at least a first one of said processors in said predetermined first set of said plurality of processors to initiate a communication to a second processor in said plurality of processors.
Claim 24
Dependent Claim
22 words
The circuitry of claim 22, further comprising: circuitry for transferring said status information from said first transfer circuitry to said control circuitry.
Claim 25
Dependent Claim
17 words
The circuitry of claim 23, wherein said circuitry for transferring said status information includes a fifo memory.
Claim 26
Dependent Claim
36 words
The circuitry of claim 1, wherein said second transfer circuitry includes circuitry to specify one of said processors in said at least second set of said plurality of processors with which a communication may be made.
Claim 27
Dependent Claim
27 words
The circuitry of claim 25, wherein said second transfer circuitry includes circuitry to detect a signal indicating that a specified processor is operable to receive a communication.
Claim 28
Dependent Claim
48 words
The circuitry of claim 1, wherein said second transfer circuitry is operable to receive a request to initiate a communication with one of said processors of said first set of said plurality of processors from a processor in said at least second set of said plurality of processors.
Claim 29
Dependent Claim
23 words
The circuitry of claim 27, wherein said second transfer circuitry is operable to initiate a communication in response to said request to initiate.
Claim 30
Dependent Claim
48 words
The circuitry of claim 1, wherein said second transfer circuitry is operable to generate a request to initiate a communication from one of said processors of said first set of said plurality of processors with a processor in said at least second set of said plurality of processors.
Claim 31
Dependent Claim
62 words
The circuitry of claim 1, wherein said first transfer circuitry includes circuitry for polling at least one of said processors in said predetermined first set of said plurality of processors to detect status information generated by a first one of said at least one of said processors in said predetermined first set of processors to initiate a communication with a second processor.
Claim 32
Dependent Claim
56 words
The circuitry of claim 1, wherein said second transfer circuitry includes circuitry for enabling a communication responsive to said first transfer circuitry polling at least one of said processors in said predetermined first set of said plurality processor to detect a signal indicating that at least one of said processors is operable to receive a communication.
Claim 33
Dependent Claim
53 words
The circuitry of claim 1, wherein said second transfer circuitry includes at least one signal line for use during communications between one or more of said processors in said predetermined first set of said plurality of processors and one or more processors in said at least second set of said plurality of processors.
Claim 34
Dependent Claim
12 words
The circuitry of claim 1, wherein said control circuitry includes a microprocessor.
Claim 35
Dependent Claim
48 words
The circuitry of claim 1, wherein said second transfer circuitry includes circuitry responsive to at least one processor in said at least second set of said plurality of processors to initiate a communication with at least one processor in said predetermined first set of said plurality of processors.
Claim 36
Dependent Claim
48 words
The circuitry of claim 1, wherein said second transfer circuitry includes circuitry responsive to at least one processor in said at least second set of said plurality of processors to receive a communication from at least one processor in said predetermined first set of said plurality of processors.
References Cited (Backward Citations)
US3803555A
Cited
US4034354A
Cited
US4084240A
Cited
US4256926A
Cited
US4564900A
Cited
US4685125A
Cited
US4614841A
Cited
US4677558A
Cited
US4730256A
Cited
US4698841A
Cited
US4783657A
Cited
US5115499A
Cited
US4885739A
Cited
US4949300A
Cited
US4875206A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-28 | 1997-08-30 | 1998-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-28 | 2001-08-30 | 2002-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-28 | 2005-08-30 | 2006-03-01 | $7700.00 | Window Closed / Lapsed |