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US5292674A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making a metal-oxide semiconductor field-effect transistor

Assignee: NEC Corp
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Filing: 1991-11-29
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Granted: 1994-03-08
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Expires: 2011-11-29
📄 Original PDF 🌐 Google Patents

Abstract

Abstract Disclosed is an improved metal oxide-semiconductor field-effect transistor having two diffused regions extending apart from under one and the other edge of the gate in the opposite directions, at least one of the diffused regions being composed of a first leastdoped, short section, a second lightly-doped, short section, and a third heavily-doped, long section. Either diffused region may be used as drain. The series-connection of least and lightly-doped sections of the same longitudinal size or depth improves the current driving capability of the semiconductor device. Also, methods of making such MOSFETs are disclosed.

Inventors

  • 👤 Kazuhiro Okabe
  • 👤 Isami Sakai

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 14:54
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 239 words
A method of making a metal-oxide semiconductor field-effect transistor comprising the steps of: preparing a semi-fabricated product comprising a semiconductor substrate of one conductivity type with a gate insulating layer formed on its top surface, and a gate built on said gate insulating layer; injecting an impurity of the other conductivity type into said semiconductor substrate perpendicular to the top surface of said semiconductor substrate to form two opposite diffusion layers of least concentration of impurity in said semiconductor substrate, extending from first and second locations under one and the other edge of said gate respectively in the opposite directions; forming a side wall surrounding said gate on said semiconductor substrate; injecting the impurity of the other conductivity type into said semiconductor substrate at a given acute angle with respect to the normal line perpendicular to the top surface of said semiconductor substrate to form two opposite diffusion layers of less concentration of impurity in said semiconductor substrate, extending short of the terminal ends of said diffusion layers of least concentration of impurity; injecting the impurity of the other conductivity type into said semiconductor substrate perpendicular to the top surface of said semiconductor substrate to form two opposite diffusion layers of relatively high concentration of impurity in said semiconductor substrate, extending from the first and second locations under one and the other edge of said side wall in the opposite directions; and forming drain, source and gate electrodes respectively.
Claim 2
Independent Claim 239 words
A method of making a metal-oxide semiconductor field-effect transistor comprising the steps of: preparing a semi-fabricated product comprising a semiconductor substrate of one conductivity type with a gate insulating layer formed on its top surface, and a gate built on said gate insulating layer; injecting an impurity of the other conductivity type into said semiconductor substrate perpendicular to the top surface of said semiconductor substrate to form two opposite diffusion layers of least concentration of impurity in said semiconductor substrate, extending from first and second locations under one and the other edge of said gate respectively in the opposite directions; forming a side wall surrounding said gate on said semiconductor substrate; injecting the impurity of the other conductivity type into said semiconductor substrate at a given acute angle with respect to the normal line perpendicular to the top surface of said semiconductor substrate to form two opposite diffusion layers of less concentration of impurity in said semiconductor substrate, extending short of the terminal ends of said diffusion layers of least concentration of impurity; injecting the impurity of the other conductivity type into said semiconductor substrate perpendicular to the top surface of said semiconductor substrate to form two opposite diffusion layers of relatively high concentration of impurity in said semiconductor substrate, extending from the first and second locations under one and the other edge of said side wall in the opposite directions; and forming drain, source and gate electrodes respectively.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-03-07 1997-09-06 1998-03-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-03-07 2001-09-06 2002-03-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-03-07 2005-09-06 2006-03-08 $7700.00 Window Closed / Lapsed

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