Data processing system which generates a waveform with improved pulse width resolution

Claim 2

A data processing system, comprising: a high resolution counter, said high resolution counter receiving a clock signal having a predetermined period and a predetermined half-period, the predetermined half-period being equal to one-half the predetermined period; wherein said high resolution counter comprises: counter means for counting, said counter means having a count value, the count value having a first portion and a second portion; compare means for comparing, said compare means being coupled to said counter means, said compare means for receiving a duty control value, the duty control value having a first portion and a second portion, said compare means for comparing the first portion of the duty control value to the first portion of the count value; and waveform means for generating an output signal, said waveform means being coupled to said compare means, if the duty control value is an even value, then the output signal transitions from a first logic state to a second logic state when the first portion of the duty control value matches the first portion of the count value, but if the duty control value is an odd value, then the output signal transitions from the first logic state to the second logic state one predetermined half-period after the first portion of the duty control value matches the first portion of the count value.

Claim 3

A data processing system according to claim 1, wherein the output signal transitions from the second logic state to the first logic state when the count value is a predetermined roll over value.

Claim 4

A data processing system according to claim 1, wherein said high resolution counter further comprises: resolution selection circuitry for selecting one of a higher resolution mode and a lower resolution mode, said counter means being incremented/decremented by ones when the lower resolution mode is selected, and said counter means being incremented/decremented by twos when the higher resolution mode is selected.

Claim 5

A data processing system according to claim 1, wherein said high resolution counter further comprises: a polarity control signal, the first logic state being a higher voltage state when said polarity control signal has a first polarity value, and the first logic state being a lower voltage state when said polarity control signal has a second polarity value.

Claim 6

The data processing system according to claim 1, wherein the high resolution counter performs one of a timer function and a serial communication function.

Claim 7

The data processing system according to claim 1 wherein the data processing system is contained on a semiconductor chip.

Claim 8

The data processing system according to claim 1, further comprising: a reset signal for forcing the output signal to an output signal reset state.

Claim 9

The data processing system according to claim 1, further comprising: a data processor, coupled to said high resolution counter, said data processor providing the duty control value to said high resolution counter; and a clock generator, coupled to said high resolution counter, said clock generator providing the clock signal to said high resolution counter.

Claim 10

The data processing system according to claim 8, wherein the data processor performs pulse width modulation of the output signal.

Claim 13

A method according to claim 10, further comprising the step of: transitioning the signal waveform from the second logic state to the first logic state when the count value is a predetermined roll over value.

Claim 14

A method according to claim 10, further comprising the step of: providing a polarity control signal, the first logic state being a higher voltage state when the polarity control signal has a first polarity value, and the first logic state being a lower voltage state when the polarity control signal has a second polarity value.

Claim 15

A method according to claim 10, further comprising the steps of: providing a reset signal; and forcing the signal waveform to a reset state when the reset signal is asserted.

Claim 16

A method according to claim 10, further comprising the step of: using the signal waveform to perform one of a timer function and a serial communication function.

Claim 17

A method according to claim 10, further comprising the steps of: calculating the duty control value in a data processor; and using the data processor to perform pulse width modulation of the signal waveform.

Claim 18

A method according to claim 10, further comprising the step of: providing a resolution control signal for selecting the integer N.

Claim 19

In a data processing system having a clock signal, the clock signal having a predetermined period and a predetermined half-period, the predetermined half-period being equal to one-half the predetermined period, a method of generating a signal waveform using the clock signal, the method comprising the steps of: storing a count value, the count value having a least significant bit and a plurality of most significant bits; receiving the clock signal; receiving a duty control value, the duty control value having a least significant bit and a plurality of most significant bits; selecting one of a lower resolution mode and a higher resolution mode; if the lower resolution mode has been selected, performing the following steps: (a) incrementing/decrementing the count value by ones using the clock signal; (b) comparing the duty control value and the count value; and (c) transitioning the signal waveform from a first logic state to a second logic state when the duty control value matches the count value; and if the higher resolution mode has been selected, performing the following steps: (i) incrementing/decrementing the counter by twos using the clock signal; (ii) comparing the plurality of most significant bits of the duty control value to the plurality of most significant bits of the count value; (iii) if the duty control value is an even value, transitioning the signal waveform from the first logic state to the second logic state when the plurality of most significant bits of the duty control value matches the plurality of most significant bits of the count value; and (iv) if the duty control value is an odd value, transitioning the signal waveform from a first logic state to a second logic state one predetermined half-period after the plurality of most significant bits of the duty control value matches the plurality of most significant bits of the count value.

Claim 20

In a data processing system having a clock signal, the clock signal having a predetermined period and a predetermined half-period, the predetermined half-period being equal to one-half the predetermined period, a method of generating a signal waveform using the clock signal, the method comprising the steps of: storing a count value, the count value having a least significant bit and a plurality of most significant bits; receiving the clock signal; receiving a duty control value, the duty control value having a least significant bit and a plurality of most significant bits; selecting one of a lower resolution mode and a higher resolution mode; if the lower resolution mode has been selected, performing the following steps: (a) incrementing/decrementing the count value by ones using the clock signal; (b) comparing the duty control value and the count value; and (c) transitioning the signal waveform from a first logic state to a second logic state when the duty control value matches the count value; and if the higher resolution mode has been selected, performing the following steps: (i) incrementing/decrementing the counter by twos using the clock signal; (ii) comparing the plurality of most significant bits of the duty control value to the plurality of most significant bits of the count value; (iii) if the duty control value is an even value, transitioning the signal waveform from the first logic state to the second logic state when the plurality of most significant bits of the duty control value matches the plurality of most significant bits of the count value; and (iv) if the duty control value is an odd value, transitioning the signal waveform from a first logic state to a second logic state one predetermined half-period after the plurality of most significant bits of the duty control value matches the plurality of most significant bits of the count value.

Claim 21

A method according to claim 17, further comprising the step of: transitioning the signal waveform from the second logic state to the first logic state when the count value is a predetermined roll over value.

Claim 22

A method according to claim 17, further comprising the step of: providing a polarity control signal, the first logic state being a higher voltage state when the polarity control signal has a first polarity value, and the first logic state being a lower voltage state when the polarity control signal has a second polarity value.

Claim 23

A method according to claim 17, further comprising the steps of: providing a reset signal; and forcing the signal waveform to a reset state when the reset signal is asserted.