PROM IC with a margin test function

Claim 2

A PROM IC comprising: a plurality of memory cells; means responsive to an address signal for selecting one of said memory cells; a reading voltage application circuit responsive to a test selection signal for switching a reading voltage to be applied to said selected one of said memory cells from a predetermined voltage to an externally supplied voltage to read an information written therein; sense circuit means for binarizing a read signal from said selected one of said memory cells; resistor circuit means included in said sense circuit means on the side of an input thereof for pulling-up a potential of said input, said resistor circuit means being responsive to said test selection signal to change its resistance value from a first value to a second value with which drive condition of current flowing through said selected memory cell becomes severe; wherein each said memory cell comprises a floating gate type transistor and wherein said second value of said resistor circuit means is smaller than said first value; and wherein said predetermined voltage applied to said gate of said transistor is 0 V and wherein said first resistance value is in a range from several hundreds k to several M ohms and said second resistance value is in a range from several k to several tens k ohms.

Claim 3

The PROM IC claimed in claim 1, wherein said resistor circuit means comprises a plurality of resistors and a transistor which is responsive to said test selection signal to turn ON or OFF to thereby change said resistance value of said resistor circuit means.

Claim 4

A PROM IC comprising: a plurality of memory cells; address decoder means responsive to an address signal for selecting one of said memory cells corresponding to said address signal; a reading voltage application circuit responsive to a test selection signal for changing said reading voltage from a standard reading voltage to an externally supplied voltage and for applying said externally supplied voltage to said memory cell selected by said address decoder means; a sense circuit including a sense amplifier and a resistor circuit arranged on the side of an input of said sense amplifier and providing a resistance value variable in response to said test selection signal, a potential of said input of said sense amplifier being pulled-up by a power source through said resistor circuit to detect an information stored in said selected memory cell and, in response to said test selection signal, change said resistance value of said resistor circuit from a first value for a usual use of said memory cell to a second value with which drive condition of current flowing through said selected memory cell becomes severe; wherein said memory cell comprises a floating gate type transistor and wherein said second resistance value of said resistor circuit is smaller than said first resistance value; and wherein said resistor circuit comprises a plurality of resistors and a transistor which is responsive to said test selection signal to turn ON or OFF to thereby change said resistance value of said resistor circuit means.

Claim 5

A PROM IC comprising: a plurality of memory cells; address decoder means responsive to an address signal for selecting one of said memory cells corresponding to said address signal; a reading voltage application circuit responsive to a test selection signal for changing said reading voltage from a standard reading voltage to an externally supplied voltage and for applying said externally supplied voltage to said memory cell selected by said address decoder means; a sense circuit including a sense amplifier and a resistor circuit arranged on the side of an input of said sense amplifier and providing a resistance value variable in response to said test selection signal, a potential of said input of said sense amplifier being pulled-up by a power source through said resistor circuit to detect an information stored in said selected memory cell and, in response to said test selection signal, change said resistance value of said resistor circuit from a first value for a usual use of said memory cell to a second value with which drive condition of current flowing through said selected memory cell becomes severe; wherein said memory cell comprises a floating gate type transistor and wherein said second resistance value of said resistor circuit is smaller than said first resistance value; and wherein said resistor circuit comprises a plurality of resistors and a transistor which is responsive to said test selection signal to turn ON or OFF to thereby change said resistance value of said resistor circuit means.

Claim 6

The PROM IC claimed in claim 3, wherein said plurality of said resistors comprise transistors, respectively.