US5298787A — Semiconductor embedded layer technology including…

Claim 1

Independent Claim 118 words

An active semiconductor device comprising: a thin metal base layer embedded in a semiconductor single crystal and providing a metal-semiconductor potential barrier between emitter and collector regions, the metal base layer having at least one opening therein through which semiconductor single crystal extends, substantially all of the openings being dimensioned such that the ratio of metal layer thickness to opening width is less than one-half to permit barrier limited current flow therethrough within an operating range of base biasing, the barrier being sufficient at some base biasing level to virtually eliminate current flow through the openings, the normalized transconductance g m /I c of the device being greater than 2 volt -1 over a range of collector current.

Claim 2

Dependent Claim 118 words

An active semiconductor device comprising: a thin metal base layer embedded in a semiconductor single crystal and providing a metal-semiconductor potential barrier between emitter and collector regions, the metal base layer having at least one opening therein through which semiconductor single crystal extends, substantially all of the openings being dimensioned such that the ratio of metal layer thickness to opening width is less than one-half to permit barrier limited current flow therethrough within an operating range of base biasing, the barrier being sufficient at some base biasing level to virtually eliminate current flow through the openings, the normalized transconductance g m /I c of the device being greater than 2 volt -1 over a range of collector current.

Claim 3

Dependent Claim 87 words

An active semiconductor device comprising: a thin metal layer embedded in semiconductor single crystal material to separate single crystal regions and form a potential barrier; the metal layer having at least one opening therein through which semiconductor single crystal material joins the crystal regions, substantially all openings in the metal layer having the same controlled width in the order of the zero bias depletion width of the barrier; and the thickness of the metal layer being in the order of 10% of the zero bias depletion width.

Claim 4

Dependent Claim 87 words

An active semiconductor device comprising: a thin metal layer embedded in semiconductor single crystal material to separate single crystal regions and form a potential barrier; the metal layer having at least one opening therein through which semiconductor single crystal material joins the crystal regions, substantially all openings in the metal layer having the same controlled width in the order of the zero bias depletion width of the barrier; and the thickness of the metal layer being in the order of 10% of the zero bias depletion width.

Claim 5

Dependent Claim 14 words

An active semiconductor device as claimed in claim 2 wherein the openings are slits.

Claim 6

Dependent Claim 33 words

An active semiconductor device as claimed in claim 3 wherein the opening widths are less than the zero bias depletion width in the semiconductor and are greater than 10% of that depletion width.

Claim 7

Dependent Claim 32 words

An active semiconductor device as claimed in claim 2 wherein the metal base layer includes at least two sets of coplanar interleaved metal fingers, each set being connected to a separate input.

Claim 8

Dependent Claim 41 words

An active semiconductor device as claimed in claim 2 wherein the total open area of the metal base layer is at least about 10 percent of the total area of the metal base layer across the active portion of the device.

Claim 9

Dependent Claim 23 words

An active semiconductor device as claimed in claim 2 wherein a plurality of openings having uniform widths are uniformly spaced across the device.

Claim 10

Dependent Claim 19 words

An active semiconductor device as claimed in claim 2 having only a single opening in the metal base layer.

Claim 11

Dependent Claim 36 words

An active semiconductor device as claimed in claim 2 wherein the opening widths are greater than 10 percent of the zero bias depletion width in the semiconductor and less than twice the zero bias depletion width.

Claim 12

Dependent Claim 21 words

An active semiconductor device as claimed in claim 9 wherein the opening widths are less than the zero bias depletion width.

Claim 13

Dependent Claim 17 words

An active semiconductor device as claimed in claim 2 including a concentration gradient in the semiconductor crystal.

Claim 14

Dependent Claim 46 words

An active semiconductor device as claimed in claim 2, in combination with a plurality of like active semiconductor devices, at least some of the interconnections between said plurality of active semiconductor devices being extensions of metal base layers and also being embedded in a semiconductor material.

Claim 15

Dependent Claim 27 words

An active semiconductor device as claimed in claim 2, in combination with a plurality of like active semiconductor devices, in a stacked configuration within a semiconductor material.

Claim 16

Dependent Claim 22 words

A plurality of active semiconductor devices as claimed in claim 13 wherein two stacked active semiconductor devices share a common semiconductor region.

Claim 17

Dependent Claim 32 words

A plurality of active semiconductor devices as claimed in claim 13 wherein at least some of the interconnections between said plurality of active semiconductor devices are completely embedded within the semiconductor material.

Claim 18

Dependent Claim 24 words

A plurality of active semiconductor devices as claimed in claim 15 wherein the embedded interconnections include extensions of metal base layers and ohmic contacts.

Claim 19

Dependent Claim 34 words

A plurality of active semiconductor devices as claimed in claim 16 wherein the semiconductor material is gallium arsenide and said plurality of active semiconductor devices are isolated by proton bombardment of the gallium arsenide.

Claim 20

Dependent Claim 36 words

A plurality of active semiconductor devices as claimed in claim 13 including a metal layer forming a Schottky barrier in an unused semiconductor region below one of said plurality of active semiconductor devices to provide isolation.

Claim 21

Dependent Claim 30 words

An active semiconductor device as claimed in claim 2, in combination with a plurality of like active semiconductor devices, including complementary devices formed in adjacent n and p type regions.

Claim 22

Dependent Claim 55 words

An active semiconductor device as claimed in claim 2 wherein substantially all current flow between the crystal regions, within an operating range of base biasing, is barrier limited current flow through the openings, the normalized transconductance g m /I c of the device being greater than 2 volts -1 over a range of collector current.

Claim 23

Dependent Claim 81 words

A transistor device comprising: single crystal semiconductor material having emitter and collector regions; and a metal base layer embedded in the single crystal semiconductor material, the metal base layer having at least one slit opening therein through which single crystal semiconductor material joins the emitter and collector regions, the width of substantially all slits in the active portion of the base layer being in the order of the zero bias depletion width of a potential barrier between the metal and semiconductor.

Claim 24

Dependent Claim 81 words

A transistor device comprising: single crystal semiconductor material having emitter and collector regions; and a metal base layer embedded in the single crystal semiconductor material, the metal base layer having at least one slit opening therein through which single crystal semiconductor material joins the emitter and collector regions, the width of substantially all slits in the active portion of the base layer being in the order of the zero bias depletion width of a potential barrier between the metal and semiconductor.

Claim 25

Dependent Claim 51 words

A transistor device as claimed in claim 3 wherein substantially all emitter-collector current flow, within an operating range of base biasing, is barrier limited current flow through the openings, the normalized transconductance g m /I c of the device being greater than 2 volts -1 over a range of collector current.

Claim 26

Dependent Claim 124 words

A transistor device comprising: a thin metal base layer embedded in a semiconductor crystal between emitter and collector contacts and providing a metal - semiconductor potential barrier; the metal base layer having a plurality of slit openings therein through which single crystal semiconductor material joins the emitter and collector regions, the width of substantially all slits in the active portion of the base layer being uniform and equal and in the order of the zero bias depletion width of the barrier; the thickness of the metal base layer being in the order of 10% of the zero bias depletion width; and substantially all emitter-collector current flow through the device being barrier limited current flow through the slits within an operating range of base biasing.

Claim 27

Dependent Claim 124 words

A transistor device comprising: a thin metal base layer embedded in a semiconductor crystal between emitter and collector contacts and providing a metal - semiconductor potential barrier; the metal base layer having a plurality of slit openings therein through which single crystal semiconductor material joins the emitter and collector regions, the width of substantially all slits in the active portion of the base layer being uniform and equal and in the order of the zero bias depletion width of the barrier; the thickness of the metal base layer being in the order of 10% of the zero bias depletion width; and substantially all emitter-collector current flow through the device being barrier limited current flow through the slits within an operating range of base biasing.

Claim 28

Dependent Claim 31 words

A transistor device as claimed in claim 23 wherein the normalized transconductance g m /I c of the device is greater than 2 volts -1 over a range of collector current.

Claim 29

Dependent Claim 54 words

An active semiconductor device comprising: an emitter semiconductor region; a collector semiconductor region; a base region including at least two sets of coplanar interleaved control fingers extending across the device between the emitter and collector regions, each set being connected to a separate input to control current flow between the emitter and base regions.

Claim 30

Dependent Claim 54 words

An active semiconductor device comprising: an emitter semiconductor region; a collector semiconductor region; a base region including at least two sets of coplanar interleaved control fingers extending across the device between the emitter and collector regions, each set being connected to a separate input to control current flow between the emitter and base regions.

Claim 31

Dependent Claim 66 words

An active semiconductor device as claimed in claim 25 wherein the interleaved fingers are metal and are spaced by a width in the order of the zero biased depletion width of a Schottky barrier formed between the fingers and the semiconductor regions and the fingers have a thickness in the order of 10 percent of the zero bias depletion width of the semiconductor between the fingers.

Claim 32

Dependent Claim 33 words

An active semiconductor device as claimed in claim 25 wherein the carrier concentration in the semiconductor regions and the finger and interspacial widths are such that the device functions as a logic circuit.

Claim 33

Dependent Claim 34 words

An active semiconductor device as claimed in claim 25 including an AC input to each of the sets of coplanar interleaved fingers such that one input modulates the output due to the other input.

Claim 34

Dependent Claim 34 words

An active semiconductor device as claimed in claim 25 including a DC input to one set of fingers to provide gain control with respect to an AC input to the other set of fingers.

Claim 35

Dependent Claim 58 words

A single semiconductor chip integrated circuit comprising a plurality of devices in a stacked configuration, at least some of the interconnections between devices being totally embedded within the semiconductor chip, the plurality of devices including devices having metal base layers embedded in the semiconductor, at least some of the embedded interconnections being extensions of said metal base layers.

Claim 36

Dependent Claim 58 words

A single semiconductor chip integrated circuit comprising a plurality of devices in a stacked configuration, at least some of the interconnections between devices being totally embedded within the semiconductor chip, the plurality of devices including devices having metal base layers embedded in the semiconductor, at least some of the embedded interconnections being extensions of said metal base layers.

Claim 37

Dependent Claim 24 words

A single semiconductor chip integrated circuit as claimed in claim 30 wherein the interconnections have openings therein through which semiconductor crystal has been grown.

Claim 38

Dependent Claim 25 words

A single semiconductor chip integrated circuit as claimed in claim 30 including interconnections which are extensions of ohmic contacts, the contacts being embedded between devices.

Claim 39

Dependent Claim 23 words

A single semiconductor chip integrated circuit as claimed in claim 30 wherein devices are isolated by heavy particle bombardment of the semiconductor material.

Claim 40

Dependent Claim 30 words

A single semiconductor chip integrated circuit as claimed in claim 30 wherein the semiconductor material is gallium arsenide and transistor devices are isolated by proton bombardment of the gallium arsenide.

Claim 41

Dependent Claim 29 words

A single semiconductor chip integrated circuit as claimed in claim 30 including current limiting devices in one layer associated in a stacked configuration with transistor devices in another layer.

Claim 42

Dependent Claim 19 words

A single semiconductor chip integrated circuit as claimed in claim 35 wherein the current limiting devices are saturated resistors.

Claim 43

Dependent Claim 29 words

A single semiconductor chip integrated circuit as claimed in claim 30 including negative resistance devices in one layer associated in a stacked configuration with transistor devices in another layer.

Claim 44

Dependent Claim 19 words

A single semiconductor chip integrated circuit as claimed in claim 30 wherein stacked devices share a common semiconductor region.

Claim 45

Dependent Claim 26 words

A single semiconductor chip integrated circuit as claimed in claim 30 including an embedded non-semiconducting layer serving as isolation for at least one of said devices.

Claim 46

Dependent Claim 25 words

A single semiconductor chip integrated circuit as claimed in claim 39 wherein the non-semiconducting layer is metal and forms a Schottky barrier with the semiconductor.

Claim 47

Dependent Claim 18 words

A single semiconductor chip integrated circuit as claimed in claim 39 wherein the non-semiconducting layer is an insulator.

Claim 48

Dependent Claim 43 words

A single semiconductor chip integrated circuit comprising a plurality of devices, including devices having metal base layers embedded in the semiconductor, at least some of the interconnections between said devices being extensions of the metal base layers totally embedded within the semiconductor chip.

Claim 49

Dependent Claim 43 words

A single semiconductor chip integrated circuit comprising a plurality of devices, including devices having metal base layers embedded in the semiconductor, at least some of the interconnections between said devices being extensions of the metal base layers totally embedded within the semiconductor chip.

Claim 50

Dependent Claim 59 words

A single semiconductor chip integrated circuit comprising a plurality of devices, at least some of the interconnections between said plurality of devices being totally embedded within the semiconductor chip, the integrated circuit further comprising an embedded metal layer which forms a Schottky barrier with the semiconductor and serves as isolation for at least one of said plurality of devices.

Claim 51

Dependent Claim 59 words

A single semiconductor chip integrated circuit comprising a plurality of devices, at least some of the interconnections between said plurality of devices being totally embedded within the semiconductor chip, the integrated circuit further comprising an embedded metal layer which forms a Schottky barrier with the semiconductor and serves as isolation for at least one of said plurality of devices.

Claim 52

Dependent Claim 39 words

A single semiconductor chip integrated circuit comprising an embedded non-semiconducting layer embedded within the semiconductor chip below a semiconductor device as isolation for the device wherein the non-semiconducting layer is metal and forms a Schottky barrier with the semiconductor.

Claim 53

Dependent Claim 39 words

A single semiconductor chip integrated circuit comprising an embedded non-semiconducting layer embedded within the semiconductor chip below a semiconductor device as isolation for the device wherein the non-semiconducting layer is metal and forms a Schottky barrier with the semiconductor.

Claim 54

Dependent Claim 25 words

A single semiconductor chip integrated circuit as claimed in claim 44 wherein the non-semiconducting layer has openings therein through which semiconductor crystal has been grown.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1997-03-28	1997-09-27	1998-03-29	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2001-03-28	2001-09-27	2002-03-29	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2005-03-28	2005-09-27	2006-03-29	$7700.00	Window Closed / Lapsed

Semiconductor embedded layer technology including permeable base transistor

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag