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US5300155A Expired / Lapsed US ⏱️ 0.0 years remaining

IC chemical mechanical planarization process incorporating slurry temperature control

Assignee: Micron Technology Inc
•
Filing: 1992-12-23
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Granted: 1994-04-05
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Expires: 2012-12-23
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Abstract

Abstract An IC chemical mechanical planarization (cmp) process incorporating slurry temperature control. Specifically, there is a VCMP process which requires small holders 18. The VCMP process incorporates small quantities of chemicals in the holder, and utilizes a system of closely regulating the heating and cooling of the chemical component of the VCMP process to increase and decrease the chemical reaction, and therefore the speed of the chemical removal of tungsten material.

Inventors

  • 👤 Gurtej S. Sandhu
  • 👤 Chris C. Yu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 03:53
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/06; H10P95/062; B; B24; B24B; B24B37/00; B24B37/04

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 189 words
A semiconductor made by a process, comprising the following steps: a) providing a semiconductor wafer having: a substrate; at least two sections of a first material (22), located upon the substrate; a second material covering the first material and substrate; b) removing the second material portion that is located on top of the first material by a temperature regulated chemical mechanical planarization (cmp) process; c) a first time period where the CMP process removing chemical has an elevated temperature to increase the rate of the second material removal; d) a second time period where the CMP process removing chemical has a lowered temperature than the elevated temperature, thus decreasing the rate of the second material removal; e) a majority of the second material being removed by the first time period, and a smaller percentage of the second material being removed by the second time period; and f) a majority of the second material being removed during the first time period chemical component of the CMP process, and a smaller percentage of the second material being removed during the first time period by the mechanical component of the CMP process,
Claim 2
Dependent Claim 189 words
A semiconductor made by a process, comprising the following steps: a) providing a semiconductor wafer having: a substrate; at least two sections of a first material (22), located upon the substrate; a second material covering the first material and substrate; b) removing the second material portion that is located on top of the first material by a temperature regulated chemical mechanical planarization (cmp) process; c) a first time period where the CMP process removing chemical has an elevated temperature to increase the rate of the second material removal; d) a second time period where the CMP process removing chemical has a lowered temperature than the elevated temperature, thus decreasing the rate of the second material removal; e) a majority of the second material being removed by the first time period, and a smaller percentage of the second material being removed by the second time period; and f) a majority of the second material being removed during the first time period chemical component of the CMP process, and a smaller percentage of the second material being removed during the first time period by the mechanical component of the CMP process,
Claim 3
Dependent Claim 15 words
The semiconductor made by the process of claim 1, wherein the second material comprises tungsten.
Claim 4
Dependent Claim 15 words
The semiconductor made by the process of claim 1, wherein the second material comprises aluminum.
Claim 5
Dependent Claim 15 words
The semiconductor made by the process of claim 1, wherein the second material comprises copper.
Claim 6
Dependent Claim 15 words
The semiconductor made by the process of claim 1, wherein the second material comprises silicon-dioxide.
Claim 7
Dependent Claim 15 words
The semiconductor made by the process of claim 1, wherein the first material comprises polysilicon.

References Cited (Backward Citations)

US3841031A Cited
US4193226A Cited
US4450652A Cited
US4811522A Cited
US4956313A Cited
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US5104828A Cited
US4992135A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-04-04 1997-10-04 1998-04-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-04-04 2001-10-04 2002-04-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-04-04 2005-10-04 2006-04-05 $7700.00 Window Closed / Lapsed

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