Method and processor for high-speed convergence factor determination

Claim 1

A numeric processor comprising: a processing platform for processing convergence factors utilizing an input signal value having other than ±∞, ±0, or Not-a-Number (NaN), for a mathematical determination of an electrical output signal, being convergent division determination/square root determination, wherein the input value is modified to a value X, such that X is limited to a range with a lower limit greater than or equal to 0.5 and an upper limit β determined, at least in part, by the mathematical determination invoked and such that X is defined as X=2 e * f, said platform comprising: A) electrical first selecting means operably coupled to receive the input signal value for selecting an input signal value other than ±∞, ±0, or NaN; B) electrical input signal value altering means being one of: B1) a read-only memory (ROM), and B2) an arithmetic logic unit (ALU), operably coupled to the first selecting means for converting a selected input signal value to a value X such that 0.5≦X<β, the respective value of β being a constant value related to the mathematical determination; C) electrical exponent means of a read-only memory (ROM) and an arithmetic logic unit (ALU), operably coupled to the input signal value altering means for selecting a value for an exponent e; D) electrical first determining means of a read-only memory (ROM) and an arithmetic logic unit (ALU), operably coupled to the input signal value altering means and the exponent means for determining a value for f, wherein f=X/2 e such that 1≦f<2 and f is represented by a series of binary bits consisting of a most significant binary bit and remaining binary bits; E) electrical locating means, operably coupled to the first determining means for placing the most significant binary bit of f, being 1, to the immediate left of a binary point with the remaining binary bits of f located to the right of the binary point; F) electrical second selecting means of a read-only memory (ROM) and an arithmetic logic unit (ALU), operably coupled to the locating means and the first determining means for selecting binary bits to the right of the binary point in accordance with the value of X and the mathematical determination; G) electrical complementing means being one of: G1) a read-only memory (ROM), and G2) an arithmetic logic unit (ALU), operably coupled to the second selecting means for determining a one's complement of the selected binary bits to the right of the binary point; H) electrical combining means being one of: H1) a read-only memory (ROM), and H2) an arithmetic logic unit (ALU), operably coupled to the complementing means for combining the most significant bit of f, being 1, with the one's complement of the selected binary bits, thereby determining f', a new value for f; I) electrical second determining means being one of: I1) a read-only memory (ROM), and I2) an arithmetic logic unit (ALU), operably coupled to the combining means for determining X', a new value for X, in electrical form such that X'=2 e * f'; and J) electrical third determining means being one of: J1) a read-only memory (ROM), and J2) an arithmetic logic unit (ALU), operably coupled to the second determining means for generating a convergence factor in electrical form such that X'=2.0-X being a new convergence factor for convergent division and X'=1.5-0.5X being a new convergence factor for square root determination.

Claim 14

A method for expediting and improving floating point computation of convergence factors 2.0-X and 1.5-0.5X for a mathematical determination using data storage means and data manipulation means of a numeric processor, the mathematical determination being convergent division or square root determination, for an input value X having other than ±∞, ±0, or NaN wherein X is limited to a certain range with a lower limit greater than or equal to 0.5 and an upper limit β determined by the mathematical determination invoked and such that X=2 e* f, said method comprising the steps of: A) storing an input value X in one or more data input devices of the numeric processor; B) determining using one or more data manipulation devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor, that the input value is not ±∞, ±0, or NaN; C) converting an input value X to a value X such that 0.5≦X<β, wherein β is a constant value related to the mathematical determination, using one or more data manipulation and storage devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor; D) selecting a value for an exponent e using one or more data manipulation and storage devices a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor; E) determining a value for f wherein f=X/2 e , using one or more data manipulation and storage devices in a read-only memory (ROM), and an arithmetic logic unit (ALU), of the numeric processor, such that 1≦f<2 and f is represented by a series of binary bits consisting of a most significant bit and remaining binary bits; F) setting the most significant bit of f to 1 with the remaining binary bits of f to the right of a binary point using one or more data manipulation and storage devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor; G) selecting binary bits to the right of the binary point in accordance with the value of X and the mathematical determination invoked using one or more data manipulation and storage devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor; H) one's complementing the selected binary bits to the right of the binary point using one or more data manipulation and storage devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor; I) combining the most significant bit of f, being 1, with the one's complement of the selected binary bits, thereby determining a new value for f, designated f' using one or more data manipulation and storage devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor; J) determining a new X, designated X', wherein X'=2 e* f' using one or more data manipulation and storage devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor; and K) generating a convergence factor Y such that Y=2.0-X' for convergent division and Y=1.5-0.5X' for square root determination using one or more data manipulation and storage devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor.

Claim 15

A method for expediting and improving floating point computation of convergence factors 2.0-X and 1.5-0.5X for a mathematical determination using data storage means and data manipulation means of a numeric processor, the mathematical determination being convergent division or square root determination, for an input value X having other than ±∞, ±0, or NaN wherein X is limited to a certain range with a lower limit greater than or equal to 0.5 and an upper limit β determined by the mathematical determination invoked and such that X=2 e* f, said method comprising the steps of: A) storing an input value X in one or more data input devices of the numeric processor; B) determining using one or more data manipulation devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor, that the input value is not ±∞, ±0, or NaN; C) converting an input value X to a value X such that 0.5≦X<β, wherein β is a constant value related to the mathematical determination, using one or more data manipulation and storage devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor; D) selecting a value for an exponent e using one or more data manipulation and storage devices a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor; E) determining a value for f wherein f=X/2 e , using one or more data manipulation and storage devices in a read-only memory (ROM), and an arithmetic logic unit (ALU), of the numeric processor, such that 1≦f<2 and f is represented by a series of binary bits consisting of a most significant bit and remaining binary bits; F) setting the most significant bit of f to 1 with the remaining binary bits of f to the right of a binary point using one or more data manipulation and storage devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor; G) selecting binary bits to the right of the binary point in accordance with the value of X and the mathematical determination invoked using one or more data manipulation and storage devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor; H) one's complementing the selected binary bits to the right of the binary point using one or more data manipulation and storage devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor; I) combining the most significant bit of f, being 1, with the one's complement of the selected binary bits, thereby determining a new value for f, designated f' using one or more data manipulation and storage devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor; J) determining a new X, designated X', wherein X'=2 e* f' using one or more data manipulation and storage devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor; and K) generating a convergence factor Y such that Y=2.0-X' for convergent division and Y=1.5-0.5X' for square root determination using one or more data manipulation and storage devices in a read-only memory (ROM) and an arithmetic logic unit (ALU), of the numeric processor.