US5305262A
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Semiconductor integrated circuit
Assignee: Kawasaki Microelectronics Inc
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Filing: 1992-09-09
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Granted: 1994-04-19
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Expires: 2012-09-09
Abstract
Abstract A semiconductor integrated circuit has a CAM structure based on nonvolatile memories which is used for forming a flexible CAM of large scale integration. The circuit includes a first memory cell for defining the electrical connection or the nonconnection between a first data line and a match line, a second memory cell for defining the electrical nonconnection or the connection between a second data line and the match line, and a selective transistor for making or breaking the connection between each of the first and the second data lines and the match line. The threshold voltage of the selective transistor has a predetermined value incorporated during the fabrication process. The semiconductor integrated circuit can electrically connect a selective word line connected to a gate electrode of the selective transistor to the match line and has a tri-state buffer for making the potential of the selective word line float. The threshold voltage of each nonvolatile memory is set at a predetermined voltage. The semiconductor integrated circuit is capable of retrieving data from a plurality of memory cells at high speed without mutual interference and is able to provide an associative memory unit for use as a high-speed, large capacity data base.
Inventors
- 👤 Masato Yoneda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:08
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; G11C15/046
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
222 words
A semiconductor integrated circuit comprising: a first memory cell for providing one of an electrical connection and an electrical nonconnection between a first data line and a match line; a second memory cell for defining one of an electrical nonconnection and an electrical connection between a second data line and said match line, wherein the first and second memory cells electrically connect the match line to at least one of the first and second data lines; selective transistors for making and breaking the electrical connection/nonconnection between each of said first and said second data lines and said match line in accordance with the definition of the electrical connections of said first and second memory cells; and a current driving type sense amplifier connected to said match line, wherein a threshold voltage of each said selective transistor has a predetermined value incorporated during a fabrication process and a gate voltage V W of each of said selective transistor satisfies the following condition at the time of retrieval operation: V.sub.t ≦V.sub.W ≦V.sub.S +V.sub.t' where: V t : threshold voltage of the selective transistor (at the time of 0 V substrate bias); V S : potential of the match line at the time of retrieval operation; V t' : threshold voltage of the selective transistor subjected to substrate bias at the time of retrieval operation.
Claim 2
Dependent Claim
222 words
A semiconductor integrated circuit comprising: a first memory cell for providing one of an electrical connection and an electrical nonconnection between a first data line and a match line; a second memory cell for defining one of an electrical nonconnection and an electrical connection between a second data line and said match line, wherein the first and second memory cells electrically connect the match line to at least one of the first and second data lines; selective transistors for making and breaking the electrical connection/nonconnection between each of said first and said second data lines and said match line in accordance with the definition of the electrical connections of said first and second memory cells; and a current driving type sense amplifier connected to said match line, wherein a threshold voltage of each said selective transistor has a predetermined value incorporated during a fabrication process and a gate voltage V W of each of said selective transistor satisfies the following condition at the time of retrieval operation: V.sub.t ≦V.sub.W ≦V.sub.S +V.sub.t' where: V t : threshold voltage of the selective transistor (at the time of 0 V substrate bias); V S : potential of the match line at the time of retrieval operation; V t' : threshold voltage of the selective transistor subjected to substrate bias at the time of retrieval operation.
Claim 3
Dependent Claim
39 words
A semiconductor integrated circuit as claimed in claim 1, wherein the voltage V t (at the time of 0 V substrate bias) at the value incorporated in said selective transistor is set higher than that of any peripheral circuit.
Claim 4
Dependent Claim
19 words
A semiconductor integrated circuit as claimed in claim 1, wherein said memory cells each comprises a nonvolatile memory element.
Claim 5
Dependent Claim
20 words
A semiconductor integrated circuit as claimed in claim 3, wherein said nonvolatile memory element is a MONOS-type nonvolatile memory element.
Claim 6
Dependent Claim
75 words
A semiconductor integrated circuit as claimed in claim 1, further comprising a plurality of retrieval memory word blocks, each of said blocks including a set of said first and second memory cells, said selective transistors and a selective word line connected to a gate electrode of each of said selective transistors for controlling said selective transistors, wherein said match line and said sense amplifier are commonly used for said plurality of retrieval memory word blocks.
Claim 7
Dependent Claim
115 words
A semiconductor integrated circuit comprising a first memory cell for defining the electrical connection or the nonconnection between a first data line and a match line, a second memory cell for defining the electrical nonconnection or the connection between a second data line and said match line, a selective transistor for making and breaking the connection between each of said first and said second data lines and said match line in accordance with the definition of the connections of said first and second memory cells, means for electrically connecting a selective word line connected to a gate electrode of said selective transistor to said match line, and means for making said selective word line afloat.
Claim 8
Dependent Claim
115 words
A semiconductor integrated circuit comprising a first memory cell for defining the electrical connection or the nonconnection between a first data line and a match line, a second memory cell for defining the electrical nonconnection or the connection between a second data line and said match line, a selective transistor for making and breaking the connection between each of said first and said second data lines and said match line in accordance with the definition of the connections of said first and second memory cells, means for electrically connecting a selective word line connected to a gate electrode of said selective transistor to said match line, and means for making said selective word line afloat.
Claim 9
Dependent Claim
26 words
A semiconductor integrated circuit as claimed in claim 6, wherein a threshold voltage of said selective transistor has a predetermined value incorporated during a fabrication process.
Claim 10
Dependent Claim
86 words
A semiconductor integrated circuit as claimed in claim 6, wherein a gate voltage V W of said selective transistor satisfies the following conditions at the time of retrieval operation: V.sub.t ≦V.sub.W ≦V.sub.H +V.sub.t' where V t : threshold voltage of the selective transistor (at the time of 0 V substrate bias); V H : H (high) potential of the data line at the time of retrieval operation; V t' : threshold voltage of the selective transistor subjected to substrate bias at the time of retrieval operation.
Claim 11
Dependent Claim
41 words
A semiconductor integrated circuit as claimed in the claim 6, wherein the threshold voltage V t (at the time of 0 V substrate bias) at the value incorporated in said selective transistor is set higher than that of any peripheral circuit.
Claim 12
Dependent Claim
19 words
A semiconductor integrated circuit as claimed in claim 7, wherein said memory cells each comprises a nonvolatile memory element.
Claim 13
Dependent Claim
20 words
A semiconductor integrated circuit as claimed in claim 10, wherein said nonvolatile memory element is a MONOS-type nonvolatile memory element.
Claim 14
Dependent Claim
74 words
A semiconductor integrated circuit as claimed in claim 6, further comprising a plurality of retrieval memory word blocks, each of said blocks including a set of said first and second memory cells, said selective transistors and said selective word line for controlling said selective transistors, wherein said match line and a potential detecting means for detecting an electric potential of the match line are commonly used for said plurality of retrieval memory word blocks.
Claim 15
Dependent Claim
228 words
A semiconductor integrated circuit comprising: a first nonvolatile memory cell for defining the electrical connection or the nonconnection between a first data line and a match line; a second nonvolatile memory cell for defining the electrical nonconnection or the connection between a second data line and said match line; and a selective word line for controlling said first and second nonvolatile memory cells, said first and second nonvolatile memory cells and said selective word line being combined into a retrieval memory word block, wherein the voltage of each signal line and the threshold voltage of each nonvolatile memory cell are so arranged as to satisfy the following equations (I) and (II) simultaneously at the time of data retrieval operation: V.sub.W -V.sub.H <V.sub.tL <V.sub.W -V.sub.L <V.sub.tH (I) V.sub.W -V.sub.S <V.sub.tL (II) where V tL : low threshold voltage of the nonvolatile memory cell; V W : potential of the selective word line at the time of retrieval operation; V tH : high threshold voltage of the nonvolatile memory cell; V H : H (high) potential of each of the data lines supplied with H (high) potential at the time of retrieval operation; V L : L (low) potential of each of the data lines supplied with L (low) potential at the time of retrieval operation; V S : potential of the match line at the time of retrieval operation.
Claim 16
Dependent Claim
228 words
A semiconductor integrated circuit comprising: a first nonvolatile memory cell for defining the electrical connection or the nonconnection between a first data line and a match line; a second nonvolatile memory cell for defining the electrical nonconnection or the connection between a second data line and said match line; and a selective word line for controlling said first and second nonvolatile memory cells, said first and second nonvolatile memory cells and said selective word line being combined into a retrieval memory word block, wherein the voltage of each signal line and the threshold voltage of each nonvolatile memory cell are so arranged as to satisfy the following equations (I) and (II) simultaneously at the time of data retrieval operation: V.sub.W -V.sub.H <V.sub.tL <V.sub.W -V.sub.L <V.sub.tH (I) V.sub.W -V.sub.S <V.sub.tL (II) where V tL : low threshold voltage of the nonvolatile memory cell; V W : potential of the selective word line at the time of retrieval operation; V tH : high threshold voltage of the nonvolatile memory cell; V H : H (high) potential of each of the data lines supplied with H (high) potential at the time of retrieval operation; V L : L (low) potential of each of the data lines supplied with L (low) potential at the time of retrieval operation; V S : potential of the match line at the time of retrieval operation.
Claim 17
Dependent Claim
30 words
A semiconductor integrated circuit as claimed in claim 13, wherein said nonvolatile memory cell is formed with a nonvolatile transistor having a threshold voltage satisfying said equations (I) and (II).
Claim 18
Dependent Claim
48 words
A semiconductor integrated circuit as claimed in claim 13, further comprising means for setting the voltages of each signal line and the threshold voltage of each nonvolatile memory cell at the time of retrieval operation so that the integrated circuit can satisfy said equations (I) and (II) simultaneously.
Claim 19
Dependent Claim
30 words
A semiconductor integrated circuit as claimed in claim 13, wherein said nonvolatile memory element is at least one selected from the group consisting of mask ROM, EPROM, EEPROM and UVEPROM.
Claim 20
Dependent Claim
39 words
A semiconductor integrated circuit as claimed in claim 13, wherein said match line and a potential detecting means for detecting an electric potential of the match line are commonly used for a plurality of said retrieval memory word blocks.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-18 | 1997-10-18 | 1998-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-18 | 2001-10-18 | 2002-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-18 | 2005-10-18 | 2006-04-19 | $7700.00 | Window Closed / Lapsed |