US5305273A
Expired / Lapsed
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Semiconductor memory device
Assignee: NEC Corp
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Filing: 1992-09-10
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Granted: 1994-04-19
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Expires: 2012-09-10
Abstract
Abstract A semiconductor memory device has a matrix of memory cells interconnected by a plurality of column and row lines to form a channel between one of the column lines and a voltage source corresponding to a specified status. A sensing circuit connects or disconnects an output node where the current is supplied from the voltage source with the input node which indicates the status of the specified memory cell. A reference voltage generation circuit generates the reference voltage. A comparison circuit generates a signal to indicate the specified status of the selected memory cell. Between the output and input nodes of the sensing circuit, a first transistor under gate control by a reverse voltage of the input node voltage is connected and between the input node of the sensing circuit and the input node of the reference voltage generation circuit, a second transistor under gate control by the reverse voltage is also provided. The column line of the selected memory cell is charged by the voltage source of the sensing circuit via the first transistor and also by the voltage source of the reference voltage generation circuit via the second transistor.
Inventors
- 👤 Toshikatsu Jinbo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 00:28
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/14; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
255 words
A semiconductor memory device comprising: memory cells in matrix connection with a plurality of column and row lines to form a channel between one of the column lines and a voltage source corresponding to a specified status, a column selection means to select any of said column lines, a row selection means to select any of said row lines, a sensing means for connecting an output node thereof with the input node thereof, said sensing means input node indicating the specified status of a memory cell selected by selection of said column and row lines, a reference voltage generation means for connecting an input node thereof, said reference voltage generation means input node being also connected to a reference memory cell through a reference memory cell selection circuit, with an output node thereof and for generating a reference voltage at said output node, and a comparison means to compare the voltage at the output node of said sensing means with the reference voltage at the output node of said reference voltage generating means and to issue a signal indicating the specified status of the selected memory cell, characterized by that a first transistor under gate control by a voltage inverse to the voltage on the input node of said sensing means, is connected between the output and input nodes of said sensing means and that a second transistor under gate control by said inverse voltage is connected between the input node of said sensing means and the input node of said reference voltage generation means.
Claim 2
Dependent Claim
255 words
A semiconductor memory device comprising: memory cells in matrix connection with a plurality of column and row lines to form a channel between one of the column lines and a voltage source corresponding to a specified status, a column selection means to select any of said column lines, a row selection means to select any of said row lines, a sensing means for connecting an output node thereof with the input node thereof, said sensing means input node indicating the specified status of a memory cell selected by selection of said column and row lines, a reference voltage generation means for connecting an input node thereof, said reference voltage generation means input node being also connected to a reference memory cell through a reference memory cell selection circuit, with an output node thereof and for generating a reference voltage at said output node, and a comparison means to compare the voltage at the output node of said sensing means with the reference voltage at the output node of said reference voltage generating means and to issue a signal indicating the specified status of the selected memory cell, characterized by that a first transistor under gate control by a voltage inverse to the voltage on the input node of said sensing means, is connected between the output and input nodes of said sensing means and that a second transistor under gate control by said inverse voltage is connected between the input node of said sensing means and the input node of said reference voltage generation means.
Claim 3
Dependent Claim
47 words
A semiconductor memory device of claim 1 wherein a third transistor under gate control by a voltage inverse to the voltage on said input node of said reference voltage generation means is connected between the output node and the input node of said reference voltage generation means.
Claim 4
Dependent Claim
24 words
A semiconductor memory device of claim 2 wherein said second transistor has a threshold value smaller than that of said first or third transistors.
Claim 5
Dependent Claim
20 words
A semiconductor memory device of claim 2 wherein said first, second and third transistors are N-channel type field effect transistors.
Claim 6
Dependent Claim
32 words
A semiconductor memory device of claim 2 wherein said first and third transistors are intrinsic transistors having a threshold voltage of about 0 V and said second transistor is an enhancement transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-04-18 | 1997-10-18 | 1998-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-18 | 2001-10-18 | 2002-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-18 | 2005-10-18 | 2006-04-19 | $7700.00 | Window Closed / Lapsed |