Data bus using open drain drivers and differential receivers together with distributed termination impedances

Claim 2

An electronic system including a plurality of circuit board modules, wherein each module is interconnected to the other modules via a data bus consisting of a plurality of conductive paths, the data bus of the type which uses distributed termination impedances, and wherein each module comprises: operating logic circuits, mounted on the module, which provide a plurality of transmit logic signals to be communicated to the logic circuits located on the other modules, and which also receive a plurality of receive logic signals from the logic circuits located on the other modules; a direct current (DC) power supply circuit, located on the module, for providing a power supply signal to the logic circuits mounted on the same module; an open drain driver transistor, connected to receive one of the transmit logic signals from the logic circuits, and connected to one of the conductive paths, to thereby forward the logic signal to another module; a termination impedance, mounted on the module, and connected between the conductive path and the power supply, such that each conductive path has a single termination impedance connected thereto in each module; a reference voltage circuit, connected to receive the power supply signal, and to generate a reference voltage; and a differential receiver, connected to receive the reference voltage and connected to one of the conductive paths, for receiving a receive logic signal from one of the other modules, and to thereby forward the receive logic signal to the operating logic circuits.

Claim 3

An electronic system as in claim 1 wherein the resistance of the termination impedance is chosen so that a minimum propagation delay is provided on the data bus both when a driver transistor in a given module drives a logic signal consisting of alternating logic levels in succession, as well as when the driver transistors in two different modules drive a given logic level in succession.

Claim 4

An electronic system as in claim 1 comprising: a clock generator, for generating a clock signal; and a driver flip flop, connected to receive the transmit logic signal and the clock signal, and to provide a latched transmit logic signal to the driver.

Claim 5

An electronic system as in claim 3 comprising: a receiver latch, connected to the differential receiver and the clock signal, and to provide a latched receive logic signal to the operating logic circuits.

Claim 6

An electronic system as in claim 3 comprising: a multiplexor, connected to receive an output enable signal, the transmit logic signal from the operating logic, and a deasserted logic signal, and connected to drive a data input of the driver flip flop, for connecting the transmit logic signal to the data input of the driver flip flop when the output enable signal is asserted, and for connecting the deasserted logic signal to the data input of the driver flip flop when the output enable signal is deasserted.

Claim 7

An electronic system as in claim 3 wherein the driver flip flop additionally has a test input which, when asserted, causes the driver transistor to deassert the conductive path to which it is connected.

Claim 8

An electronic system as in claim 3 comprising: an inverter formed by a pull-up transistor and a pull-down transistor, connected between the driver flip flop and the driver transistor.

Claim 9

An electronic system as in claim 7 wherein the gate width of the inverter transistors are tapered to match the driver transistor, and the gate widths of output transistors in the driver flip flop are tapered to match the inverter transistors.

Claim 10

An electronic system including a plurality of circuit board modules, wherein each module is interconnected to the other modules via a data bus consisting of a plurality of conductive paths, the data bus of the type which makes use of distributed termination impedances, and wherein each module comprises: operating logic circuits, mounted on the module, which provide a plurality of transmit logic signals to be communicated to the logic circuits located on the other modules, and which also receive a plurality of receive logic signals from the logic circuits located on the other modules; a multiplexor, connected to receive an output enable signal, to receive one of the transmit logic signals from the operating logic circuits, and a deasserted logic signal, for providing the transmit logic signal as a multiplexor output signal when the output enable signal is asserted, and for providing the deasserted logic signal as a multiplexor output signal when the output enable signal is deasserted; a clock generator, for generating a clock signal; a driver flip flop, connected to receive one of the transmit logic signals from the operating logic circuits at a data input and the clock signal, and to provide a latched transmit logic signal; a direct current (DC) power supply circuit, located on the module, for providing a termination voltage to the logic circuits mounted on the same module; an open drain driver transistor, connected to receive the latched transmit logic signal, and connected to one of the conductive paths, to thereby forward the latched transmit logic signal to another module; a termination impedance, mounted on the module, and connected between the conductive path and the termination voltage, such that the conductive path has a single termination impedance connected thereto in each module, the resistance of the termination impedance being chosen so that a minimum propagation delay is provided on the conductive path both when the driver transistor in a given module drives a logic signal consisting of alternating logic levels in succession, as well as when the driver transistors in two different modules drive a given logic level in succession; a reference voltage circuit, connected to receive the termination voltage, and to generate a reference voltage; a differential receiver, connected to receive the reference voltage and connected to one of the conductive paths, for receiving a receive logic signal from one of the other modules, and to thereby provide a differential logic signal; and a receiver latch, connected to the differential receiver and the clock signal, to provide a latched receive logic signal to the operating logic circuits.

Claim 11

An electronic system including a plurality of circuit board modules, wherein each module is interconnected to the other modules via a data bus consisting of a plurality of conductive paths, the data bus of the type which makes use of distributed termination impedances, and wherein each module comprises: operating logic circuits, mounted on the module, which provide a plurality of transmit logic signals to be communicated to the logic circuits located on the other modules, and which also receive a plurality of receive logic signals from the logic circuits located on the other modules; a multiplexor, connected to receive an output enable signal, to receive one of the transmit logic signals from the operating logic circuits, and a deasserted logic signal, for providing the transmit logic signal as a multiplexor output signal when the output enable signal is asserted, and for providing the deasserted logic signal as a multiplexor output signal when the output enable signal is deasserted; a clock generator, for generating a clock signal; a driver flip flop, connected to receive one of the transmit logic signals from the operating logic circuits at a data input and the clock signal, and to provide a latched transmit logic signal; a direct current (DC) power supply circuit, located on the module, for providing a termination voltage to the logic circuits mounted on the same module; an open drain driver transistor, connected to receive the latched transmit logic signal, and connected to one of the conductive paths, to thereby forward the latched transmit logic signal to another module; a termination impedance, mounted on the module, and connected between the conductive path and the termination voltage, such that the conductive path has a single termination impedance connected thereto in each module, the resistance of the termination impedance being chosen so that a minimum propagation delay is provided on the conductive path both when the driver transistor in a given module drives a logic signal consisting of alternating logic levels in succession, as well as when the driver transistors in two different modules drive a given logic level in succession; a reference voltage circuit, connected to receive the termination voltage, and to generate a reference voltage; a differential receiver, connected to receive the reference voltage and connected to one of the conductive paths, for receiving a receive logic signal from one of the other modules, and to thereby provide a differential logic signal; and a receiver latch, connected to the differential receiver and the clock signal, to provide a latched receive logic signal to the operating logic circuits.

Claim 12

An electronic system as in claim 9 wherein the driver flip flop additionally has a test input which, when asserted, causes the driver transistor to deassert the conductive path to which it is connected.

Claim 13

An electronic system as in claim 9 comprising: an inverter formed by a pull-up transistor and a pull-down transistor, connected between the driver flip flop and the driver transistor.

Claim 14

A bus node for connecting to other bus nodes via a data bus consisting of a plurality of conductive paths, the data bus of the type which uses distributed termination impedances, wherein each bus node comprises: an open drain driver transistor, connected to one of the conductive paths; means for providing a bus termination voltage; a termination impedance, located at the bus node, and connected between the conductive path and the termination voltage, such that each conductive path has a single termination impedance connected thereto at each bus node; a reference voltage circuit, connected to the termination supply voltage, and to generate a reference voltage; and a differential receiver, connected to receive the reference voltage and connected to one of the conductive paths.

Claim 15

A bus node for connecting to other bus nodes via a data bus consisting of a plurality of conductive paths, the data bus of the type which uses distributed termination impedances, wherein each bus node comprises: an open drain driver transistor, connected to one of the conductive paths; means for providing a bus termination voltage; a termination impedance, located at the bus node, and connected between the conductive path and the termination voltage, such that each conductive path has a single termination impedance connected thereto at each bus node; a reference voltage circuit, connected to the termination supply voltage, and to generate a reference voltage; and a differential receiver, connected to receive the reference voltage and connected to one of the conductive paths.

Claim 16

A bus node as in claim 12 wherein the resistance of the termination impedance is chosen so that a minimum propagation delay is provided on the conductive paths both when a driver transistor in a given node drives a logic signal consisting of alternating logic levels in successive bus cycles, as well as when the driver transistors in two different bus nodes drive an identical logic level in successive bus cycles.

Claim 17

A bus node as in claim 12 comprising: a clock generator, for generating a clock signal; and a driver flip flop, connected to receive a transmit logic signal and the clock signal, and to provide a latched transmit logic signal to the driver.

Claim 18

A bus node as in claim 14 comprising: a receiver latch, connected to the differential receiver and the clock signal, and to provide a latched receive signal and an output.

Claim 19

A bus node as in claim 14 comprising: a multiplexor, connected to receive an output enable signal, the transmit logic signal, and a deasserted logic signal, and connected to drive a data input of the driver flip flop, for connecting the transmit logic signal to the data input of the driver flip flop when the output enable signal is asserted, and for connecting the deasserted logic signal to the data input of the driver flip flop when the output enable signal is deasserted.

Claim 20

A bus node as in claim 14 wherein the driver flip flop includes a test input which, when asserted, causes the driver transistor to deassert the conductive path to which it is connected.

Claim 21

A bus node as in claim 14 comprising: an inverter formed by a pull-up transistor and a pull-down transistor, connected between the driver flip flop and the driver transistor.

Claim 22

A bus node as in claim 18 wherein the gate width of the inverter transistors are tapered to match the driver transistor, and the gate widths of output transistors in the driver flip flop are tapered to match the inverter transistors.

Claim 25

A method as in claim 20 wherein the resistance of the termination impedance is chosen so that a minimum propagation delay is provided on the data bus both when a driver transistor in a given module drives a logic signal consisting of alternating logic levels in succession, as well as when the driver transistors in two different modules drive a given logic level in succession.

Claim 26

A method as in claim 20 comprising: generating a clock signal; and latching the transmit logic signal in synchronism with the clock signal.

Claim 27

A method as in claim 22 comprising: latching the receive logic signal in synchronism with the clock signal.

Claim 28

A method as in claim 22 comprising: selecting the transmit logic signal as an operating logic signal when an output enable signal is asserted, and selecting a deasserted logic signal as the transmit logic signal when the output enable signal is deasserted.

Claim 29

A method as in claim 22 wherein the transmit logic signal may additionally be selected as the deasserted logic signal when a test input signal is asserted.

Claim 30

A method as in claim 22 comprising: inverting the transmit logic signal before forwarding it to the driver transistor.

Claim 31

A method as in claim 26 wherein transmitted logic signal is inverted by forwarding it though a pair of inverter transistors, and a gate width of the inverter transistors is tapered to optimize driving the load presented by the gate of the driver transistor.

Claim 34

A method as in claim 28 wherein the resistance of the termination impedance is chosen so that a minimum propagation delay is provided on the conductive paths both when a driver drives a logic signal consisting of alternating logic levels in successive bus cycles, as well as when drivers in two different bus nodes drive an identical logic level in successive bus cycles.

Claim 35

A method as in claim 28 comprising: generating a clock signal; and latching a driver input signal in synchronism with the clock signal.

Claim 36

A method as in claim 28 comprising: generating a receive clock signal; and latching the receive logic signal in synchronism with the clock signal.

Claim 37

A method as in claim 28 comprising: selecting a deasserted logic signal as a driver input signal when an output enable signal is asserted, and for otherwise selecting a transmit logic signal as a driver input signal when the output enable signal is deasserted.

Claim 38

A method as in claim 28 comprising: selecting the deasserted logic signal as a driver signal input when a test signal is asserted.

Claim 39

A method as in claim 32 comprising: inverting the driver input signal.

Claim 40

A method as in claim 34 wherein the step of inverting is provided by a pair of inverter transistors, and the gate width of the inverter transistors is tapered to optimize driving the load presented by the gate of a transistor in the driver.