US5319388A
Expired / Lapsed
US
⏱️ 0.0 years remaining
VGA controlled having frame buffer memory arbitration and method therefor
Assignee: Philips Semiconductors Inc
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Filing: 1992-06-22
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Granted: 1994-06-07
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Expires: 2012-06-22
Abstract
Abstract An improved VGA Controller with Arbitration Logic and method therefor is provided to enhance system performance by efficiently using the minimum amount of bus bandwidth required. This Controller includes a bus to the Frame Buffer that either the system CPU or the Display Controller may access and control. The Display Controller includes a Display FIFO which stores display data from the Frame Buffer for the Display Controller to use. This Display FIFO coupled with the Arbitration Logic makes it possible for the Display Controller to continue to output display data even when the system CPU is accessing the display data in the Frame Buffer. The Arbitration Logic attempts to keep the Display FIFO as full as possible such that a bus request by the system CPU can be immediately granted when received.
Inventors
- 👤 Phillip E. Mattison
- 👤 Kenneth P. Caviasca
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 05:51
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/34; G09G3/36; G09G5/00; G09G5/001; G06; G06F; G06F13/00; G06F13/14; G06F13/36
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
456 words
A VGA Controller for driving an external display device comprising, in combination: a Frame Buffer memory having a Frame Buffer Bus; Display Controller means coupled to said Frame Buffer memory for reading display data contained in said Frame Buffer memory and for converting said display data to a serial format for driving said external display device; Central Processing Unit (CPU) means having a CPU Data Bus and having a Bus Arbitration coupled to said Display Controller means for allowing said CPU means to read and write said display data into said Frame Buffer memory; Controller Bus means comprising a single bus directly connected to said CPU Data Bus of said CPU means, to said Frame Buffer Bus of said Frame Buffer memory, and to said Display Controller means for providing a path to transfer said display data between said CPU means and said Frame Buffer memory and for providing a path to transfer said display data between said Frame Buffer memory and said Display Controller means; and said Display Controller means comprising, in combination: Arbitration Logic means coupled to said Bus Arbitration of said CPU means for determining when said CPU means may take control of said Controller Bus means in order to transfer said display data between said CPU means and said Frame Buffer memory; Display First-In First-Out (FIFO) means coupled to said Controller Bus means and to said Arbitration Logic means for permitting said Arbitration Logic means to transfer said display data from said Frame buffer memory into said Display FIFO means; and Video Shift Logic means electrically coupled to said Arbitration Logic means and to said Display FIFO means for permitting said Arbitration Logic means to transfer said display data stored in said Display FIFO means to said Video Shift Logic means which converts said display data to said serial format and shifts said display data out of said Display Controller means directly out of said VGA Controller means, which data in said serial format is used for driving said external display device; said Arbitration Logic means causing said display data in said Frame Buffer memory to be transferred to said Display FIFO means when said CPU means is not requesting control of said Controller Bus means by asserting the proper status on said Bus Arbitration of said CPU means; said Arbitration Logic means continuing to transfer said display data in said Frame Buffer memory to said Display FIFO means until said Display FIFO means is filled to a preset level; and said Arbitration Logic means granting control of said Controller Bus means to said CPU means when said CPU means requests said control by asserting the proper status on said Bus Arbitration, provided said Display FIFO is filled to said preset level.
Claim 2
Dependent Claim
456 words
A VGA Controller for driving an external display device comprising, in combination: a Frame Buffer memory having a Frame Buffer Bus; Display Controller means coupled to said Frame Buffer memory for reading display data contained in said Frame Buffer memory and for converting said display data to a serial format for driving said external display device; Central Processing Unit (CPU) means having a CPU Data Bus and having a Bus Arbitration coupled to said Display Controller means for allowing said CPU means to read and write said display data into said Frame Buffer memory; Controller Bus means comprising a single bus directly connected to said CPU Data Bus of said CPU means, to said Frame Buffer Bus of said Frame Buffer memory, and to said Display Controller means for providing a path to transfer said display data between said CPU means and said Frame Buffer memory and for providing a path to transfer said display data between said Frame Buffer memory and said Display Controller means; and said Display Controller means comprising, in combination: Arbitration Logic means coupled to said Bus Arbitration of said CPU means for determining when said CPU means may take control of said Controller Bus means in order to transfer said display data between said CPU means and said Frame Buffer memory; Display First-In First-Out (FIFO) means coupled to said Controller Bus means and to said Arbitration Logic means for permitting said Arbitration Logic means to transfer said display data from said Frame buffer memory into said Display FIFO means; and Video Shift Logic means electrically coupled to said Arbitration Logic means and to said Display FIFO means for permitting said Arbitration Logic means to transfer said display data stored in said Display FIFO means to said Video Shift Logic means which converts said display data to said serial format and shifts said display data out of said Display Controller means directly out of said VGA Controller means, which data in said serial format is used for driving said external display device; said Arbitration Logic means causing said display data in said Frame Buffer memory to be transferred to said Display FIFO means when said CPU means is not requesting control of said Controller Bus means by asserting the proper status on said Bus Arbitration of said CPU means; said Arbitration Logic means continuing to transfer said display data in said Frame Buffer memory to said Display FIFO means until said Display FIFO means is filled to a preset level; and said Arbitration Logic means granting control of said Controller Bus means to said CPU means when said CPU means requests said control by asserting the proper status on said Bus Arbitration, provided said Display FIFO is filled to said preset level.
Claim 3
Independent Claim
464 words
A method for providing a VGA Controller for driving an external display device comprising the steps of: providing a Frame Buffer memory having a Frame Buffer Bus; providing Display Controller means coupled to said Frame Buffer memory for reading display data contained in said frame Buffer Memory and for converting said display data to a serial format for driving said external display device; providing Central Processing Unit (CPU) means having a CPU Data Bus and having a Bus Arbitration coupled to said Display Controller means for allowing said CPU means to read and write said display data into said Frame Buffer memory; providing Controller Bus means comprising a single bus directly connected to said CPU Data Bus of said CPU means, to said Frame Buffer Bus of said Frame Buffer memory, and to said Display Controller means for providing a path to transfer said display data between said CPU means and said Frame Buffer memory, and for providing a path to transfer said display data between said Frame Buffer memory and said Display Controller means; and said Display Controller means comprising, in combination: Arbitration Logic means coupled to said Bus Arbitration of said CPU means for determining when said CPU means may take control of said Controller Bus means in order to transfer said display data between said CPU means and said Frame Buffer memory; Display First-In First-Out (FIFO) means coupled to said Controller Bus means and to said Arbitration Logic means for permitting said Arbitration Logic means to transfer said display data from said Frame Buffer memory into said Display FIFO means; and Video Shift Logic means electrically coupled to said Arbitration Logic means and to said Display FIFO means for permitting said Arbitration Logic means to transfer said display data stored in said Display FIFO means to said Video Shift Logic means which converts said display to said serial format and shifts said display data out of said Display Controller means directly out of said VGA controller means, which data in said serial format is used for driving said external display device; said Arbitration Logic means causing said display data in said Frame Buffer memory to be transferred to said Display FIFO means when said CPU means is not requesting control of said Controller Bus means by asserting the proper status on said Bus Arbitration of said CPU means; said Arbitration Logic means continuing to transfer and display data in said Frame Buffer memory to said Display FIFO means until said Display FIFO means is filled to a reset level; and said Arbitration Logic means granting control of said Controller Bus means to said CPU means when said CPU means requests said control by asserting the proper status on said Bus Arbitration, provided said Display FIFO is filled to said preset level.
Claim 4
Independent Claim
464 words
A method for providing a VGA Controller for driving an external display device comprising the steps of: providing a Frame Buffer memory having a Frame Buffer Bus; providing Display Controller means coupled to said Frame Buffer memory for reading display data contained in said frame Buffer Memory and for converting said display data to a serial format for driving said external display device; providing Central Processing Unit (CPU) means having a CPU Data Bus and having a Bus Arbitration coupled to said Display Controller means for allowing said CPU means to read and write said display data into said Frame Buffer memory; providing Controller Bus means comprising a single bus directly connected to said CPU Data Bus of said CPU means, to said Frame Buffer Bus of said Frame Buffer memory, and to said Display Controller means for providing a path to transfer said display data between said CPU means and said Frame Buffer memory, and for providing a path to transfer said display data between said Frame Buffer memory and said Display Controller means; and said Display Controller means comprising, in combination: Arbitration Logic means coupled to said Bus Arbitration of said CPU means for determining when said CPU means may take control of said Controller Bus means in order to transfer said display data between said CPU means and said Frame Buffer memory; Display First-In First-Out (FIFO) means coupled to said Controller Bus means and to said Arbitration Logic means for permitting said Arbitration Logic means to transfer said display data from said Frame Buffer memory into said Display FIFO means; and Video Shift Logic means electrically coupled to said Arbitration Logic means and to said Display FIFO means for permitting said Arbitration Logic means to transfer said display data stored in said Display FIFO means to said Video Shift Logic means which converts said display to said serial format and shifts said display data out of said Display Controller means directly out of said VGA controller means, which data in said serial format is used for driving said external display device; said Arbitration Logic means causing said display data in said Frame Buffer memory to be transferred to said Display FIFO means when said CPU means is not requesting control of said Controller Bus means by asserting the proper status on said Bus Arbitration of said CPU means; said Arbitration Logic means continuing to transfer and display data in said Frame Buffer memory to said Display FIFO means until said Display FIFO means is filled to a reset level; and said Arbitration Logic means granting control of said Controller Bus means to said CPU means when said CPU means requests said control by asserting the proper status on said Bus Arbitration, provided said Display FIFO is filled to said preset level.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-06 | 1997-12-06 | 1998-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-06 | 2001-12-06 | 2002-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-06 | 2005-12-06 | 2006-06-07 | $7700.00 | Window Closed / Lapsed |