US5331597A
Expired / Lapsed
US
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Semiconductor nonvolatile memory apparatus including threshold voltage shift circuitry
Assignee: Toshiba Corp
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Filing: 1991-03-29
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Granted: 1994-07-19
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Expires: 2011-03-29
Abstract
Abstract A semiconductor nonvolatile memory apparatus is composed of differential cells in which data can be written electrically, data reading sense amplifiers for reading data from these cells, and threshold voltage shift checking sense amplifier connected to respective sense inputs of the sense amplifiers through selecting switching elements and checking threshold voltages of respective transistors within the differential type cells. According to this semiconductor nonvolatile memory apparatus, data can be read out at high speed without increasing the chip size.
Inventors
- 👤 Sumio Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:24
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/062; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
217 words
A semiconductor memory device, comprising: a differential memory cell for storing data and including a first transistor having a first threshold voltage and a second transistor having a second threshold voltage; a first bit line connected to said first transistor; a second bit line connected to said second transistor; a first column selecting transistor having a first terminal connected to said first bit line and a gate thereof receiving a column selection signal; a second column selecting transistor having a first terminal connected to said second bit line and a gate thereof receiving said column selection signal; a data reading sense amplifier for reading data from said memory cell and having a first input connected to a second terminal of said first column selecting transistor and a second input connected to a second terminal of said second column selecting transistor; threshold voltage shift detecting circuitry including first and second threshold voltage shift detecting sense amplifiers for detecting threshold voltage shifts of said first and second transistors, respectively; a first switching element connected in series between said first threshold voltage shift checking circuit and said first input of said data reading sense amplifier; and a second switching element connected in series between said threshold voltage shift checking circuit and said second input of said data reading sense amplifier.
Claim 2
Dependent Claim
217 words
A semiconductor memory device, comprising: a differential memory cell for storing data and including a first transistor having a first threshold voltage and a second transistor having a second threshold voltage; a first bit line connected to said first transistor; a second bit line connected to said second transistor; a first column selecting transistor having a first terminal connected to said first bit line and a gate thereof receiving a column selection signal; a second column selecting transistor having a first terminal connected to said second bit line and a gate thereof receiving said column selection signal; a data reading sense amplifier for reading data from said memory cell and having a first input connected to a second terminal of said first column selecting transistor and a second input connected to a second terminal of said second column selecting transistor; threshold voltage shift detecting circuitry including first and second threshold voltage shift detecting sense amplifiers for detecting threshold voltage shifts of said first and second transistors, respectively; a first switching element connected in series between said first threshold voltage shift checking circuit and said first input of said data reading sense amplifier; and a second switching element connected in series between said threshold voltage shift checking circuit and said second input of said data reading sense amplifier.
Claim 3
Dependent Claim
20 words
The semiconductor memory device according to claim 1, further comprising: a data writing circuit connected to said differential memory cell.
Claim 4
Dependent Claim
72 words
The semiconductor memory device according to claim 2, further comprising a multi-layer wiring including metal wirings and high resistance wirings, wherein said high resistance wirings are connected to said data writing circuit and to said differential memory cell to allow the writing of data from said data writing circuit to said differential memory cell and wherein said metal wirings are connected to said data reading sense amplifier to read out data therefrom.
Claim 5
Dependent Claim
43 words
The semiconductor memory device according to claim 1, in which said first transistor is in an ON state, said second transistor is placed in an OFF state, and said second bit line is in an inverted potential relation with said first bit line.
Claim 6
Dependent Claim
97 words
The semiconductor memory device according to claim 4, further comprising means, including said first and second switching elements, for selectively comparing voltages at a plurality of resistive loads, and in which in addition to said differential memory cell, a dummy cell is connected to a third load having a resistance value which is smaller than respective resistance values of a first and second load, said first and second loads being respectively connected to first and second nodes which are connected to said first and second bit lines, and said third load is taken as a reference voltage.
Claim 7
Dependent Claim
64 words
The semiconductor memory device according to claim 1, wherein said first and second threshold voltage shift detecting sense amplifier and a sense amplifier reference voltage generating circuit are located at a first location and said data reading sense amplifier, said first and second switching elements, and said first and second column selecting transistors are located at a second location different from said first location.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-18 | 1998-01-17 | 1998-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-18 | 2002-01-17 | 2002-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-18 | 2006-01-17 | 2006-07-19 | $7700.00 | Window Closed / Lapsed |