Self-timed mesh routing chip with data broadcasting

Claim 2

In a mesh comprising a plurality of processor nodes, a method for broadcasting a message from a first processor node to at least two processor nodes comprising the steps of: coupling a message from a first processor node to a first message routing means, said message comprising a plurality of data words, said plurality of data words comprising a first data word and a second data word, said first data word comprising a plurality of bits specifying a first displacement with respect to said first processor node in a first dimension in said mesh, a first sign bit specifying a direction of travel in said first dimension, and a first broadcast bit specifying whether said message would be broadcast to a plurality of processor nodes in said first dimension; said second data word comprising a plurality of bits specifying a second displacement with respect to said first processor node in a second dimension in said mesh, a second sign bit specifying a direction of travel in said second dimension, and a second broadcast bit specifying whether said message should be broadcast to a plurality of processor nodes in said second dimension; selectively broadcasting said message from said first message routing means to said at least two processor nodes through at least two message routing means, each of said at least two message routing means being coupled to a corresponding one of said at least two processor nodes, if only said first broadcast bit is set, said at least two processor nodes being disposed in said first dimension at said second displacement; if only said second broadcast bit is set, said at least two processor nodes being disposed in said second dimension at said first displacement; if said first and second broadcast bits are set, said at least two processor nodes being disposed in a matrix in said first and second dimensions, the matrix being defined by the first processor node, the first displacement in the direction specified by the first sign bit, and the second displacement in the direction specified by the second sign bit.

Claim 3

The method as provided in claim 1, wherein each of said at least two message routing means through which said message is broadcast comprise at least one a synchronous FIFO, at least one data word of said message passing through each FIFO.

Claim 4

The method as provided in claim 1, wherein said first data word and said second data word are stripped off said message before being coupled to said at least two processor nodes.

Claim 5

A self-timed message routing system for broadcasting messages in a mesh of processor nodes, said system comprising: a plurality of message routing means, each of said message routing means coupled to a processor node in said mesh, said plurality of message routing means comprising a first message routing means coupled to a first processor node in said mesh, said first message routing means comprising means for receiving a message from said first processor node, said message comprising a plurality of data words, said plurality of data words including a first data word and a second data word, said first data word comprising a plurality of bits specifying a first displacement with respect to said processor node in a first dimension in said mesh, a first sign bit specifying a direction of travel in said first dimension, and a first broadcast bit specifying whether said message should be broadcast to a plurality of processor nodes in said first dimension; said second data word comprising a plurality of bits specifying a second displacement with respect to said processor node in a second dimension in said mesh, a second sign bit specifying a direction of travel in said second dimension, and a second broadcast bit specifying whether said message should be broadcast to a plurality of processor nodes in said second dimension; wherein said message is selectively broadcast from said first processor node to at least two processor nodes through said plurality of message routing means, if only said first broadcast bit is set, said at least two processor nodes being disposed in said first dimension at said second displacement; if only said second broadcast bit is set, said at least two processor nodes being disposed in said second dimension at said first displacement; if said first and second broadcast bits are set, said at least two processor nodes being disposed in a matrix in said first and second dimensions, the matrix being defined by the first processor node, the first displacement in the direction specified by the first sign bit, and the second displacement in the direction specified by the second sign bit.

Claim 6

A self-timed message routing system for broadcasting messages in a mesh of processor nodes, said system comprising: a plurality of message routing means, each of said message routing means coupled to a processor node in said mesh, said plurality of message routing means comprising a first message routing means coupled to a first processor node in said mesh, said first message routing means comprising means for receiving a message from said first processor node, said message comprising a plurality of data words, said plurality of data words including a first data word and a second data word, said first data word comprising a plurality of bits specifying a first displacement with respect to said processor node in a first dimension in said mesh, a first sign bit specifying a direction of travel in said first dimension, and a first broadcast bit specifying whether said message should be broadcast to a plurality of processor nodes in said first dimension; said second data word comprising a plurality of bits specifying a second displacement with respect to said processor node in a second dimension in said mesh, a second sign bit specifying a direction of travel in said second dimension, and a second broadcast bit specifying whether said message should be broadcast to a plurality of processor nodes in said second dimension; wherein said message is selectively broadcast from said first processor node to at least two processor nodes through said plurality of message routing means, if only said first broadcast bit is set, said at least two processor nodes being disposed in said first dimension at said second displacement; if only said second broadcast bit is set, said at least two processor nodes being disposed in said second dimension at said first displacement; if said first and second broadcast bits are set, said at least two processor nodes being disposed in a matrix in said first and second dimensions, the matrix being defined by the first processor node, the first displacement in the direction specified by the first sign bit, and the second displacement in the direction specified by the second sign bit.

Claim 7

The system as provided in claim 4, wherein each of said message routing means comprises at least one a synchronous FIFO, at least one data word of said message passing through each FIFO.

Claim 8

The system as provided in claim 5, wherein each of said message routing means further comprises a first decrementer means for decrementing said first displacement.

Claim 9

The system as provided in claim 6, wherein each of said message routing means further comprises a second decrementer means for decrementing said second displacement prior to outputting said message.

Claim 10

The system as provided in claim 7, wherein each of said message routing means further comprises a first stripping means for stripping said first word from said message prior to outputting said message to one of said processor nodes.

Claim 11

The system as provided in claim 8, wherein each of said message routing means further comprises a second stripping means for stripping said second word from said message prior to outputting said message to one of said processor nodes.

Claim 12

A message routing chip for routing messages in a two-dimensional mesh of at least one processor node, each of said messages comprising a plurality of data words including a first data word, said first data word including a first broadcast bit, said message routing chip comprising: a first input port for inputting messages traveling in a first direction in a first dimension of said two-dimensional mesh; a first output port for outputting messages to be routed in said first direction; a second output port for outputting messages to said processor node associated with the message routing chip; a first self-timed pipeline circuit for routing messages from said first input port to said first output port; a second self-timed pipeline circuit for routing messages from said first input port to said second output port; wherein said first self-timed pipeline circuit and said second self-timed pipeline circuit comprise separate and distinct pipeline circuits, said first and second self-timed pipeline circuits routing a message from said first input port to both said first output port and said second output port if said first broadcast bit is set.

Claim 13

A message routing chip for routing messages in a two-dimensional mesh of at least one processor node, each of said messages comprising a plurality of data words including a first data word, said first data word including a first broadcast bit, said message routing chip comprising: a first input port for inputting messages traveling in a first direction in a first dimension of said two-dimensional mesh; a first output port for outputting messages to be routed in said first direction; a second output port for outputting messages to said processor node associated with the message routing chip; a first self-timed pipeline circuit for routing messages from said first input port to said first output port; a second self-timed pipeline circuit for routing messages from said first input port to said second output port; wherein said first self-timed pipeline circuit and said second self-timed pipeline circuit comprise separate and distinct pipeline circuits, said first and second self-timed pipeline circuits routing a message from said first input port to both said first output port and said second output port if said first broadcast bit is set.

Claim 14

The message routing chip for routing messages as provided in claim 10, the plurality of data words including a second data word, said second data word including a second broadcast bit, the message routing chip further comprising: a third output port for outputting messages to be routed in a first direction in a second dimension; a third self-timed pipeline circuit for routing messages from said first input port to said third output port; wherein said third self-timed pipeline circuit is a separate and distinct pipeline circuit from said second pipeline circuit, second and third self-timed pipeline circuits routing a message from said first input port to said second and third output ports if said second broadcast bit is set.

Claim 15

The message routing chip for routing messages as provided in claim 10, wherein said first self-timed pipeline circuit includes a first stripper block for stripping the first word from messages prior to routing said messages to said first output port.

Claim 16

The message routing chip for routing messages as provided in claim 10, wherein said second self-timed pipeline circuit includes a second stripper block for stripping the first word from messages prior to routing said messages to said second output port.

Claim 17

The message routing chip for routing messages as provided in claim 11, wherein said third self-timed pipeline circuit includes a third stripper block for stripping the second word from messages prior to routing said messages to said third output port.

Claim 18

A message routing chip for routing messages in a two-dimensional mesh of processor nodes, said two-dimensional mesh having a first dimension and a second dimension, each of said messages comprising a plurality of data words including a first data word, said message routing chip comprising: a first dimension routing circuit for routing in said first dimension said message; a change of dimension routing circuit coupled to said first dimension routing circuit for changing the dimension in which said message is routed from said first dimension to said second dimension; a second dimension routing circuit separate and distinct from said first dimension routing circuit coupled to said change of dimension routing circuit for routing said message in said second dimension; wherein said first dimension routing circuit includes means for coupling said message from said first dimension routing circuit to said change of dimension routing circuit in the event that said first word of said message is in a first predetermined state, said first predetermined state indicating that said message has completed routing in said first dimension.

Claim 19

A message routing chip for routing messages in a two-dimensional mesh of processor nodes, said two-dimensional mesh having a first dimension and a second dimension, each of said messages comprising a plurality of data words including a first data word, said message routing chip comprising: a first dimension routing circuit for routing in said first dimension said message; a change of dimension routing circuit coupled to said first dimension routing circuit for changing the dimension in which said message is routed from said first dimension to said second dimension; a second dimension routing circuit separate and distinct from said first dimension routing circuit coupled to said change of dimension routing circuit for routing said message in said second dimension; wherein said first dimension routing circuit includes means for coupling said message from said first dimension routing circuit to said change of dimension routing circuit in the event that said first word of said message is in a first predetermined state, said first predetermined state indicating that said message has completed routing in said first dimension.

Claim 20

The message routing chip for routing messages as provided in claim 15, wherein said first dimension routing circuit receives said message from either a first direction or a second direction in said first dimension, wherein said means for coupling said message from said first dimension routing circuit to said change of dimension routing circuit comprises: a first self-timed pipeline means for coupling said message received from said first direction to said change of dimension routing circuit; and a second self-timed pipeline means for coupling said message received from said second direction to said change of dimension routing circuit.

Claim 21

The message routing chip for routing messages as provided in claim 16, wherein: said first self-timed pipeline means includes a first stripper block for stripping the first word from said message received from said first direction prior to coupling said message to said change of dimension routing circuit; and said second self-timed pipeline means includes a second stripper block for stripping the first word from said message received from said second direction prior to coupling said message to said change of dimension routing circuit.