US5336986A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage regulator for field programmable gate arrays
Assignee: Crosspoint Solutions Inc
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Filing: 1992-02-07
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Granted: 1994-08-09
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Expires: 2012-02-07
Abstract
Abstract A voltage regulator especially adaptable for use with field-programmable gate arrays (FPGA). The voltage regulator is configurable as a true voltage regulator or, alternatively, as a pseudo-voltage regulator. The voltage regulator includes circuitry to rapidly generate an operating voltage for the core or nucleus logic elements. Additional circuitry is provided to reduce the steady-state power consumption once the operating voltage is reached. To compensate for die-to-die variations, additional circuitry is also provided to adjust the compensation delays or switching rates.
Inventors
- 👤 Gary L. Allman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:47
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/262; G05F3/30; H03F3/45179; H03F3/45183; H03F3/45188; H03F2203/00; H03F2203/45; H03F2203/45302; H03F2203/45508; H03F2203/45654; H03F2203/45674
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
108 words
A semiconductor device having a plurality of core logic elements, comprising: a voltage regulator means, adapted to receive an external voltage and a reference-level voltage, for generating a first voltage having a magnitude between said external voltage and said reference-level voltage; a core logic power supply means for generating a second voltage, said second voltage having a magnitude between said external voltage and said reference-level voltage; and selection means for supplying said first voltage to said core logic elements in response to one state of a control signal and for supplying said second voltage to said core logic elements in response to another state of said control signal.
Claim 2
Dependent Claim
108 words
A semiconductor device having a plurality of core logic elements, comprising: a voltage regulator means, adapted to receive an external voltage and a reference-level voltage, for generating a first voltage having a magnitude between said external voltage and said reference-level voltage; a core logic power supply means for generating a second voltage, said second voltage having a magnitude between said external voltage and said reference-level voltage; and selection means for supplying said first voltage to said core logic elements in response to one state of a control signal and for supplying said second voltage to said core logic elements in response to another state of said control signal.
Claim 3
Dependent Claim
30 words
The semiconductor device of claim 1 wherein said first voltage is regulated and said second voltage is obtained from a resistor divider network having said external voltage as an input.
Claim 4
Dependent Claim
21 words
The semiconductor device of claim 1 wherein said selection means disables said voltage regulator means upon selection of said second voltage.
Claim 5
Dependent Claim
24 words
The semiconductor device of claim 1 wherein said core logic power supply means further comprises means for adjusting the magnitude of said second voltage.
Claim 6
Dependent Claim
35 words
The semiconductor device of claim 1 wherein said voltage regulator means comprises a first operational transconductance amplifier circuit having an output connected to a plurality of source followers and a pair of input cascode transistors.
Claim 7
Dependent Claim
35 words
The semiconductor device of claim 5 further comprising means for increasing the output slew-rate of said voltage regulator means during power-up by temporarily increasing current drive to a capacitance associated with said core logic elements.
Claim 8
Dependent Claim
37 words
The semiconductor device of claim 6 wherein said means for increasing the output slew-rate comprises a second operational transconductance amplifier circuit having an output connected in parallel with the output of said first operational transconductance amplifier circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |