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US5337274A Expired / Lapsed US ⏱️ 0.0 years remaining

Nonvolatile semiconductor memory device having adjacent memory cells and peripheral transistors separated by field oxide

Assignee: Rohm Co Ltd
•
Filing: 1993-01-14
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Granted: 1994-08-09
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Expires: 2013-01-14
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Abstract

Abstract The drain region of a memory cell transistor is constituted of a drain diffusion layer and a p - diffusion layer to provide a steep gradient of the impurity concentration. The source region of the memory cell transistor is constituted of a source diffusion layer and an n - diffusion layer to provide a gentle gradient of the impurity concentration. The LDD structure is employed in the source and drain regions of a peripheral transistor.

Inventors

  • 👤 Hiroshi Ohji

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 00:28
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10B; H10B41/00; H10B41/40

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 242 words
A nonvolatile semiconductor memory device comprising a semiconductor substrate of a first conductivity type, a memory cell transistor including a floating gate structure having a floating gate separated from the semiconductor substrate by a gate oxide film and including first source and drain diffusion layers formed in the semiconductor substrate on opposite sides of the floating gate structure and having a high impurity concentration of a second conductivity type, a second source diffusion layer in the semiconductor substrate adjacent to the first source diffusion layer having a low impurity concentration of the second conductivity type, and a second drain diffusion layer int he semiconductor substrate adjacent to the first drain diffusion layer and having a low impurity concentration of the first conductivity type, a peripheral transistor formed adjacent to the memory cell transistor having a gate electrode spaced from the semiconductor substrate by a gate oxide film, and first source and drain diffusion layers formed in the semiconductor substrate on opposite sides of the gate electrode, each having a high impurity concentration of the second conductivity type, and a second source diffusion layer and a second drain diffusion layer in the semiconductor substrate adjacent to the first source diffusion layer and the first drain diffusion layer, respectively, in the peripheral transistor, each having a low impurity concentration of the second conductivity type, and a field oxide film separating the diffusion layers of the memory cell transistor from those of the peripheral transistor.
Claim 2
Dependent Claim 242 words
A nonvolatile semiconductor memory device comprising a semiconductor substrate of a first conductivity type, a memory cell transistor including a floating gate structure having a floating gate separated from the semiconductor substrate by a gate oxide film and including first source and drain diffusion layers formed in the semiconductor substrate on opposite sides of the floating gate structure and having a high impurity concentration of a second conductivity type, a second source diffusion layer in the semiconductor substrate adjacent to the first source diffusion layer having a low impurity concentration of the second conductivity type, and a second drain diffusion layer int he semiconductor substrate adjacent to the first drain diffusion layer and having a low impurity concentration of the first conductivity type, a peripheral transistor formed adjacent to the memory cell transistor having a gate electrode spaced from the semiconductor substrate by a gate oxide film, and first source and drain diffusion layers formed in the semiconductor substrate on opposite sides of the gate electrode, each having a high impurity concentration of the second conductivity type, and a second source diffusion layer and a second drain diffusion layer in the semiconductor substrate adjacent to the first source diffusion layer and the first drain diffusion layer, respectively, in the peripheral transistor, each having a low impurity concentration of the second conductivity type, and a field oxide film separating the diffusion layers of the memory cell transistor from those of the peripheral transistor.

References Cited (Backward Citations)

US4939558A Cited
US5257095A Cited
US4928156A Cited
US5032881A Cited
US5210436A Cited
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US5124780A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-08-08 1998-02-07 1998-08-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-08-08 2002-02-07 2002-08-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-08-08 2006-02-07 2006-08-09 $7700.00 Window Closed / Lapsed

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