Semiconductor memory device and operating method

Claim 2

A semiconductor memory device formed on a semiconductor substrate comprising: voltage converting means for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage; storage means, coupled to said voltage converting means and driven by said internal power supply voltage, for storing data; substrate bias generating means, coupled to said voltage converting means and driven by a drive voltage, for generating from said drive voltage a substrate bias voltage for retaining said semiconductor substrate at a constant voltage; and switching means, coupled to said substrate bias voltage generating means and said voltage converting means, for selectively switching the drive voltage to said substrate bias generating means between said external power supply voltage and said internal power supply voltage, depending on whether said storage means is in an active state or in a standby state.

Claim 3

The semiconductor memory device according to claim 1, wherein said switching means applies said external power supply voltage as a drive voltage to said substrate bias generating means when said storage means is in an active state, and applies said internal power supply voltage as a drive voltage to said substrate bias generating means when said storage means is in a standby state.

Claim 4

The semiconductor memory device according to claim 1, wherein said substrate bias generating means includes a first substrate bias generating means driven by said external power supply voltage, and a second substrate bias generating means driven by said internal power supply voltage, and said switching means activates said first substrate bias generating means and inactivates said second substrate bias generating means when said storage means is in an active state, and inactivates said first substrate bias generating means and activates said second substrate bias generating means when said storage means is in a standby state.

Claim 5

A semiconductor memory device formed on a semiconductor substrate comprising: voltage converting means for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage; storage means, coupled to said voltage converting means and driven by said internal power supply voltage, for storing data; substrate bias generating means, coupled to said voltage converting means and driven by a drive voltage, for generating from said drive voltage a substrate bias voltage for retaining said semiconductor substrate at a constant voltage; wherein said substrate bias generating means comprises a first substrate bias generating means driven by said external power supply voltage, and second substrate bias generating means driven by said internal power supply voltage, said second substrate bias generating means being always in an active state, and switching means activates said first substrate bias generating means when said storage means is in an active state, and inactivates said first substrate bias generating means when said storage means is in a standby state.

Claim 6

A semiconductor memory device formed on a semiconductor substrate comprising: voltage converting means for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage; storage means, coupled to said voltage converting means and driven by said internal power supply voltage, for storing data; substrate bias generating means, coupled to said voltage converting means and driven by a drive voltage, for generating from said drive voltage a substrate bias voltage for retaining said semiconductor substrate at a constant voltage; wherein said substrate bias generating means comprises a first substrate bias generating means driven by said external power supply voltage, and second substrate bias generating means driven by said internal power supply voltage, said second substrate bias generating means being always in an active state, and switching means activates said first substrate bias generating means when said storage means is in an active state, and inactivates said first substrate bias generating means when said storage means is in a standby state.

Claim 7

The semiconductor memory device according to claim 1, wherein said storage means receives an externally applied control signal, said storage means being in an active state when said control signal is in a first state, and being in a standby state when said control signal is in a second state, and said switching means switches a drive voltage of said substrate bias generating means in response to the state of said control signal.

Claim 8

The semiconductor memory device according to claim 5, wherein said storage means comprises a dynamic random access memory, and said control signal comprises a row address strobe signal.

Claim 9

The semiconductor memory device according to claim 1, further comprising further substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating the substrate bias, and level detecting means for detecting a level of the substrate bias generated by said further substrate bias generating means, and activating said further substrate bias generating means until said substrate bias attains a predetermined level, and thereafter inactivating said further substrate bias generating means.

Claim 10

The semiconductor memory device according to claim 7, wherein said substrate bias generating means comprises capacitance means having a predetermined capacitance value, and said further substrate bias generating means comprises capacitance means having a larger capacitance value than said predetermined capacitance value.

Claim 11

The semiconductor memory device according to claim 2, further comprising further substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating the substrate bias, and level detecting means for detecting the substrate bias generated by said further substrate bias generating means, to activate said further substrate bias generating means until said substrate bias attains a predetermined level, and thereafter inactivate said further substrate bias generating means, wherein said switching means applies said external power supply voltage as a drive voltage to said further substrate bias generating means when said storage means is in an active state, and applies said internal power supply voltage as a drive voltage to said further substrate bias generating means when said storage means is in a standby state.

Claim 12

The semiconductor memory device according to claim 9, wherein said substrate bias generating means comprises capacitance means having a predetermined capacitance value, and said further substrate bias generating means comprises capacitance means having a larger capacitance value than said predetermined capacitance value.

Claim 13

The semiconductor memory device according to claim 3, further comprising further substrate bias generating means driven by said external power supply voltage for generating the substrate bias, and level detecting means for detecting a level of the substrate bias generated by said further substrate bias generating means, to activate said further substrate bias generating means until said substrate bias attains a predetermined level, and thereafter inactivate said further substrate bias generating means.

Claim 14

The semiconductor memory device according to claim 11, wherein each of said first and second substrate bias generating means comprises capacitance means having a predetermined capacitance value, and said further substrate bias generating means comprises capacitance means having a larger capacitance value than said predetermined capacitance value.

Claim 15

The semiconductor memory device according to claim 4, further comprising first further substrate bias generating means driven by said external power supply voltage for generating the substrate bias, first level detecting means for detecting a level of the substrate bias generated by said first further substrate bias generating means to activate said first further substrate bias generating means until said substrate bias attains a predetermined level when said storage means is in an active state, second further substrate bias generating means driven by said internal power supply voltage for generating the substrate bias, and second level detecting means for detecting a level of the substrate bias generated by said second further substrate bias generating means to activate said second further substrate bias generating means until said substrate bias attains a predetermined level, and thereafter to inactivate said second further substrate bias generating means.

Claim 16

The semiconductor memory device according to claim 13, wherein each of said first and second further substrate bias generating means comprises capacitance means having a predetermined capacitance value, and each of said first and second further substrate bias generating means comprises capacitance means having a larger capacitance value than said predetermined capacitance value.

Claim 19

The operating method according to claim 15, wherein said switching step comprises applying said external power supply voltage as a drive voltage to said substrate bias generating means when said storage means is in an active state, and applying said internal power supply voltage as a drive voltage to said substrate bias generating means when said storage means is in a standby state.

Claim 20

The operating method according to claim 15, wherein said substrate bias generating means comprises first substrate bias generating means driven by said external power supply voltage, and second substrate bias generating means driven by said internal power supply voltage, and said switching step comprises activating said first substrate bias generating means and inactivating said second substrate bias generating means when said storage means is an active state, and inactivating said first substrate bias generating means and activating said second substrate bias generating means when said storage means is in a standby state.

Claim 23

A semiconductor memory device formed on a semiconductor substrate comprising: converting means for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage; storage means driven by said internal power supply voltage for storing data; substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating a substrate bias for retaining said semiconductor substrate at a constant voltage, said substrate bias generating means comprising: a first substrate bias generating means driven by said external power supply voltage, and a second substrate bias generating means driven by said internal power supply voltage; and switching means for switching a drive voltage of said substrate bias generating means between said external power supply voltage and said internal power supply voltage, depending on whether said storage means is in an active state or in a standby state, wherein said switching means activates said first substrate bias generating means and inactivates said second substrate bias generating means when said storage means is in an active state, and inactivates said first substrate bias generating means and activates said second substrate bias generating means when said storage means is in a standby state.

Claim 24

A semiconductor memory device formed on a semiconductor substrate comprising: converting means for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage; storage means driven by said internal power supply voltage for storing data; substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating a substrate bias for retaining said semiconductor substrate at a constant voltage, said substrate bias generating means comprising: a first substrate bias generating means driven by said external power supply voltage, and a second substrate bias generating means driven by said internal power supply voltage; and switching means for switching a drive voltage of said substrate bias generating means between said external power supply voltage and said internal power supply voltage, depending on whether said storage means is in an active state or in a standby state, wherein said switching means activates said first substrate bias generating means and inactivates said second substrate bias generating means when said storage means is in an active state, and inactivates said first substrate bias generating means and activates said second substrate bias generating means when said storage means is in a standby state.

Claim 25

A semiconductor memory device formed on a semiconductor substrate comprising: converting means for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage; storage means driven by said internal power supply voltage for storing data; substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating a substrate bias for retaining said semiconductor substrate at a constant voltage, said substrate bias generating means comprising: a first substrate bias generating means driven by said external power supply voltage, and second substrate bias generating means driven by said internal power supply voltage; and switching means for switching a drive voltage of said substrate bias generating means between said external power supply voltage and said internal power supply voltage, depending on whether said storage means is in an active state or in a standby state, wherein said second substrate bias generating means being always in an active state, and said switching means activates said first substrate bias generating means when said storage means is in an active state, and inactivates said first substrate bias generating means when said storage means is in a standby state.

Claim 26

A semiconductor memory device formed on a semiconductor substrate comprising: converting means for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage; storage means driven by said internal power supply voltage for storing data; substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating a substrate bias for retaining said semiconductor substrate at a constant voltage, said substrate bias generating means comprising: a first substrate bias generating means driven by said external power supply voltage, and second substrate bias generating means driven by said internal power supply voltage; and switching means for switching a drive voltage of said substrate bias generating means between said external power supply voltage and said internal power supply voltage, depending on whether said storage means is in an active state or in a standby state, wherein said second substrate bias generating means being always in an active state, and said switching means activates said first substrate bias generating means when said storage means is in an active state, and inactivates said first substrate bias generating means when said storage means is in a standby state.

Claim 27

A semiconductor memory device formed on a semiconductor substrate comprising: converting means for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage; storage means driven by said internal power supply voltage for storing data; substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating a substrate bias for retaining said semiconductor substrate at a constant voltage; and switching means for switching a drive voltage of said substrate bias generating means between said external power supply voltage and said internal power supply voltage, depending on whether said storage means is in an active state or in a standby state, wherein said storage means receives an externally applied control signal, said storage means being in an active state when said control signal is in a first state, and being in a standby state when said control signal is in a second state, and said switching means switches a drive voltage of said substrate bias generating means in response to the state of said control signal.

Claim 28

A semiconductor memory device formed on a semiconductor substrate comprising: converting means for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage; storage means driven by said internal power supply voltage for storing data; substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating a substrate bias for retaining said semiconductor substrate at a constant voltage; and switching means for switching a drive voltage of said substrate bias generating means between said external power supply voltage and said internal power supply voltage, depending on whether said storage means is in an active state or in a standby state, wherein said storage means receives an externally applied control signal, said storage means being in an active state when said control signal is in a first state, and being in a standby state when said control signal is in a second state, and said switching means switches a drive voltage of said substrate bias generating means in response to the state of said control signal.

Claim 29

The semiconductor memory device according to claim 21, wherein said storage means comprises a dynamic random access memory, and said control signal comprises a row address strobe signal.

Claim 30

A semiconductor memory device formed on a semiconductor substrate comprising: converting means for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage; storage means driven by said internal power supply voltage for storing data; substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating a substrate bias for retaining said semiconductor substrate at a constant voltage; switching means for switching a drive voltage of said substrate bias generating means between said external power supply voltage and said internal power supply voltage, depending on whether said storage means is in an active state or in a standby state; further substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating the substrate bias; and level detecting means for detecting a level of the substrate bias generated by said further substrate bias generating means, and activating said further substrate bias generating means until said substrate bias attains a predetermined level, and thereafter inactivating said further substrate bias generating means.

Claim 31

A semiconductor memory device formed on a semiconductor substrate comprising: converting means for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage; storage means driven by said internal power supply voltage for storing data; substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating a substrate bias for retaining said semiconductor substrate at a constant voltage; switching means for switching a drive voltage of said substrate bias generating means between said external power supply voltage and said internal power supply voltage, depending on whether said storage means is in an active state or in a standby state; further substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating the substrate bias; and level detecting means for detecting a level of the substrate bias generated by said further substrate bias generating means, and activating said further substrate bias generating means until said substrate bias attains a predetermined level, and thereafter inactivating said further substrate bias generating means.

Claim 32

The semiconductor memory device according to claim 23, wherein said substrate bias generating means comprises capacitance means having a predetermined capacitance value, and said further substrate bias generating means comprises capacitance means having a larger capacitance value than said predetermined capacitance value.

Claim 33

A semiconductor memory device formed on a semiconductor substrate comprising: converting means for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage; storage means driven by said internal power supply voltage for storing data; substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating a substrate bias for retaining said semiconductor substrate at a constant voltage; switching means for switching a drive voltage of said substrate bias generating means between said external power supply voltage and said internal power supply voltage, depending on whether said storage means is in an active state or in a standby state; further substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating the substrate bias; and level detecting means for detecting the substrate bias generated by said further substrate bias generating means, to activate said further substrate bias generating means until said substrate bias attains a predetermined level, and thereafter inactivate said further substrate bias generating means, wherein said switching means applies said external power supply voltage as a drive voltage to said substrate bias generating means when said storage means is in an active state, and applies said internal power supply voltage as a drive voltage to said substrate bias generating means when said storage means is in a standby state and said switching means applies said external power supply voltage as a driven voltage to said further substrate bias generating means when said storage means is in an active state, and applies said internal power supply voltage as a drive voltage to said further substrate bias generating means when said storage means is in a standby state.

Claim 34

A semiconductor memory device formed on a semiconductor substrate comprising: converting means for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage; storage means driven by said internal power supply voltage for storing data; substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating a substrate bias for retaining said semiconductor substrate at a constant voltage; switching means for switching a drive voltage of said substrate bias generating means between said external power supply voltage and said internal power supply voltage, depending on whether said storage means is in an active state or in a standby state; further substrate bias generating means driven by said external power supply voltage or said internal power supply voltage for generating the substrate bias; and level detecting means for detecting the substrate bias generated by said further substrate bias generating means, to activate said further substrate bias generating means until said substrate bias attains a predetermined level, and thereafter inactivate said further substrate bias generating means, wherein said switching means applies said external power supply voltage as a drive voltage to said substrate bias generating means when said storage means is in an active state, and applies said internal power supply voltage as a drive voltage to said substrate bias generating means when said storage means is in a standby state and said switching means applies said external power supply voltage as a driven voltage to said further substrate bias generating means when said storage means is in an active state, and applies said internal power supply voltage as a drive voltage to said further substrate bias generating means when said storage means is in a standby state.

Claim 35

The semiconductor memory device according to claim 25, wherein said substrate bias generating means comprises capacitance means having a predetermined capacitance value, and said further substrate bias generating means comprises capacitance means having a larger capacitance value than said predetermined capacitance value.

Claim 36

The semiconductor memory device according to claim 19, further comprising further substrate bias generating means driven by said external power supply voltage for generating the substrate bias, and level detecting means for detecting a level of the substrate bias generated by said further substrate bias generating means, to activate said further substrate bias generating means until said substrate bias attains a predetermined level, and thereafter inactivate said further substrate bias generating means.

Claim 37

The semiconductor memory device according to claim 27, wherein each of said first and second substrate bias generating means comprises capacitance means having a predetermined capacitance value, and said further substrate bias generating means comprises capacitance means having a larger capacitance value than said predetermined capacitance value.

Claim 38

A semiconductor memory device formed on a semiconductor substrate comprising: converting means for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage; storage means driven by said internal power supply voltage for storing data; substrate bias generating means for generating a substrate bias far retaining said semiconductor substrate at a constant voltage; first further substrate bias generating means driven by said external power supply voltage for generating the substrate bias; first level detecting means for detecting a level of the substrate bias generated by said first further substrate bias generating means to activate said first further substrate bias generating means until said substrate bias attains a predetermined level when said storage means is in an activate state; second further substrate bias generating means driven by said internal power supply voltage for generating the substrate bias; second level detecting means for detecting a level of the substrate bias generated by said second further substrate bias generating means to activate said second further substrate bias generating means until said substrate bias attains a predetermined level, and thereafter to inactivate said second further substrate bias generating means; and switching means for selectively activating said first further substrate bias generating means in response to the state of an externally applied control signal, and wherein said storage means receives said externally applied control signal, said storage means being in an active state when said control signal is in a first state, and being in a standby state when said control signal is in a second state

Claim 39

A semiconductor memory device formed on a semiconductor substrate comprising: converting means for converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage; storage means driven by said internal power supply voltage for storing data; substrate bias generating means for generating a substrate bias far retaining said semiconductor substrate at a constant voltage; first further substrate bias generating means driven by said external power supply voltage for generating the substrate bias; first level detecting means for detecting a level of the substrate bias generated by said first further substrate bias generating means to activate said first further substrate bias generating means until said substrate bias attains a predetermined level when said storage means is in an activate state; second further substrate bias generating means driven by said internal power supply voltage for generating the substrate bias; second level detecting means for detecting a level of the substrate bias generated by said second further substrate bias generating means to activate said second further substrate bias generating means until said substrate bias attains a predetermined level, and thereafter to inactivate said second further substrate bias generating means; and switching means for selectively activating said first further substrate bias generating means in response to the state of an externally applied control signal, and wherein said storage means receives said externally applied control signal, said storage means being in an active state when said control signal is in a first state, and being in a standby state when said control signal is in a second state

Claim 40

The semiconductor memory device according to claim 29, wherein each of said first and second further substrate bias generating means comprises capacitance means having a predetermined capacitance value, and each of said first and second further substrate bias generating means comprises capacitance means having a larger capacitance value than said predetermined capacitance value.

Claim 41

An operating method of a semiconductor memory device comprising storage means and substrate bias generating means formed on a semiconductor substrate comprising the steps of: converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage, and switching a drive voltage of said substrate bias generating means between said external power supply voltage and said internal power supply voltage, depending on whether said storage means is in an active state or in a standby state, wherein said substrate bias generating means comprises first substrate bias generating means driven by said external power supply voltage, and second substrate bias generating means driven by said internal power supply voltage, and said switching step comprises activating said first substrate bias generating means and inactivating said second substrate bias generating means when said storage means is an active state, and inactivating said first substrate bias generating means and activating said second substrate bias generating means when said storage means is in a standby state.

Claim 42

An operating method of a semiconductor memory device comprising storage means and substrate bias generating means formed on a semiconductor substrate comprising the steps of: converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage, and switching a drive voltage of said substrate bias generating means between said external power supply voltage and said internal power supply voltage, depending on whether said storage means is in an active state or in a standby state, wherein said substrate bias generating means comprises first substrate bias generating means driven by said external power supply voltage, and second substrate bias generating means driven by said internal power supply voltage, and said switching step comprises activating said first substrate bias generating means and inactivating said second substrate bias generating means when said storage means is an active state, and inactivating said first substrate bias generating means and activating said second substrate bias generating means when said storage means is in a standby state.

Claim 43

An operating method of a semiconductor memory device comprising storage means end substrate baas generating means formed on a semiconductor substrate, said substrate bias generating means comprising a first substrate bias generating means driven by an external power supply voltage, and a second substrate bias generating means driven by an internal power supply voltage, said second substrate bias generating means being always in an active state, said method comprising the steps of: converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage, and activating said first substrate bias generating means when said storage means is in an active state, and inactivating said first substrate bias generating means when said storage means is in a standby state.

Claim 44

An operating method of a semiconductor memory device comprising storage means end substrate baas generating means formed on a semiconductor substrate, said substrate bias generating means comprising a first substrate bias generating means driven by an external power supply voltage, and a second substrate bias generating means driven by an internal power supply voltage, said second substrate bias generating means being always in an active state, said method comprising the steps of: converting an external power supply voltage to an internal power supply voltage lower than the external power supply voltage, and activating said first substrate bias generating means when said storage means is in an active state, and inactivating said first substrate bias generating means when said storage means is in a standby state.