Semiconductor memory device having ferroelectric film

Claim 2

A nonvolatile semiconductor memory device comprising: a memory cell, including a storing field effect transistor having a ferroelectric gate film formed on a semiconductor substrate, and a gate electrode formed on the ferroelectric gate, a reading transistor connected in series to said storing field effect transistor and a writing and erasing transistor connected to the gate electrode of said storing field effect transistor; writing means for writing data to be written into said memory cell by making said writing and erasing transistor conductive and applying a writing voltage corresponding to the data to be written to the gate electrode of said storing field effect transistor through said writing and erasing transistor so as to invert a direction of a polarization of said ferroelectric gate film or retain the polarization in an initial direction in accordance with the data to be written; reading means for reading from said memory cell data to be read, said reading means reading the data to be read by making said reading transistor conductive and checking whether a series circuit of said storing field effect transistor and said reading transistor is conductive or not; and erasing means for erasing from said memory cell data to be erased, said erasing means erasing the data to be erased by applying an erasing electric field to said ferroelectric gate film to turn the polarization to a specified direction.

Claim 3

A nonvolatile semiconductor memory device according to claim 1, wherein said writing and erasing transistor is electrically insulated from said semiconductor substrate.

Claim 4

A nonvolatile semiconductor memory device according to claim 2, wherein said writing and erasing transistor is a thin film transistor having its channel, drain and source made by selectively applying impurities to a semiconductor thin film.

Claim 5

A nonvolatile semiconductor memory device according to claim 3, wherein said reading transistor includes an impurity region formed on the semiconductor substrate; and the channel of said thin film transistor is provided on said impurity region with an insulating film intervening between them.

Claim 6

A nonvolatile semiconductor memory device according to claim 1, wherein said writing and erasing transistor is formed on said semiconductor substrate.

Claim 7

A nonvolatile semiconductor memory device according to claim 1, wherein said storing field effect transistor is formed in a well made in said semiconductor substrate.

Claim 8

A nonvolatile semiconductor memory device according to claim 1, wherein a pair of impurity regions are formed in the semiconductor substrate, and a gate of said storing field effect transistor and a gate of said reading transistor are provided between the pair of impurity regions.

Claim 9

A nonvolatile semiconductor memory device according to claim 1, wherein said reading means includes means for applying a specified potential to said storing field effect transistor from a side of said storing field effect transistor opposite to said reading transistor, and means for detecting a variation of a potential of said reading transistor at a side of said reading transistor opposite to said storing field effect transistor.

Claim 10

A nonvolatile semiconductor memory device according to claim 1, wherein said writing and erasing transistor is electrically insulated from said semiconductor substrate; and said erasing means makes said writing and erasing transistor conductive and applies an erasing voltage to the gate electrode of said storing field effect transistor through said writing and erasing transistor to turn the polarization of said ferroelectric gate film to the specified direction.

Claim 11

A nonvolatile semiconductor memory device according to claim 9, wherein said erasing voltage has a polarity reverse to the polarity of said writing voltage.

Claim 12

A nonvolatile semiconductor memory device according to claim 1, wherein said writing and erasing transistor is formed in said semiconductor substrate; and said erasing means makes said writing and erasing transistor conductive, applies a specified potential to the gate electrode of said storing field effect transistor through said writing and erasing transistor, and applies the erasing voltage to said storing field effect transistor from a side of said storing field effect transistor opposite to said reading transistor to turn the polarization of said ferroelectric gate film to the specified direction.

Claim 13

A nonvolatile semiconductor memory device according to claim 11, wherein said erasing voltage is voltage sufficiently higher than said writing voltage.

Claim 14

A nonvolatile semiconductor memory device according to claim 1, wherein said storing field effect transistor is formed in a well made in said semiconductor substrate; and said erasing means makes said writing and erasing transistor conductive, applies a specified potential to the gate electrode of said storing field effect transistor through said writing and erasing transistor, and applies an erasing voltage to said well to turn the polarization of said ferroelectric gate film to the specified direction.

Claim 15

A nonvolatile semiconductor memory device according to claim 13, wherein said erasing voltage is almost equal to said writing voltage.

Claim 16

A nonvolatile semiconductor memory device according to claim 1, wherein a gate of the writing and erasing transistor is connected to a drain of the reading transistor.

Claim 17

A nonvolatile memory device according to claim 1, wherein the initial direction is the specified direction and said writing means applies the writing voltage to the gate electrode of said storing field effect transistor through said writing and erasing transistor so as to retain the polarization of said ferroelectric gate film in the specified direction or invert the direction of polarization, in accordance with the data to be written.

Claim 18

A nonvolatile memory device according to claim 16, wherein the writing voltage to invert the direction of polarization is opposite in polarity to the erasing voltage, and the writing voltage to retain the polarization in the specified direction is intermediate of the writing voltage to invert the direction of polarization and the erasing voltage.

Claim 19

A nonvolatile memory device according to claim 17, wherein the writing voltage to retain the polarization in the specified direction is a ground potential.

Claim 20

A nonvolatile semiconductor memory device, comprising: a semiconductor substrate; a plurality of memory cells aligned in rows and columns in a matrix array on said semiconductor substrate, each memory cell including: a storing field effect transistor having a ferroelectric gate film formed on said semiconductor substrate, a gate electrode formed on the ferroelectric gate film, a reading transistor connected in series to said storing field effect transistor, and a writing and erasing transistor connected to the gate electrode of said storing field effect transistor; a separate corresponding reading word line for each row of said rows, each reading word line connected to a gate of said reading transistor in each memory cell of the memory cells aligned in the row to which the reading word line corresponds; a separate corresponding writing and erasing word line for each row of said rows, each writing and erasing word line connected to said writing and erasing transistor at a side of said writing and erasing transistor opposite to said storing field effect transistor in each memory cell of the memory cells aligned in the row to which the writing and erasing word line corresponds; a separate corresponding bit line for each column of said columns, each bit line connected to said reading transistor at a side of said reading transistor opposite to said storing field effect transistor in each memory cell of the memory cells aligned in said each column; means for applying a voltage provided on any one of said bit lines, to a gate of said writing and erasing transistor of each of the memory cells aligned in the column to which the one bit line corresponds; writing means for selecting any first selected memory cell from among the memory cells of the matrix array and writing data in the first selected memory cell, said writing means including: means for applying a first specified voltage to the bit line connected to the first selected memory cell to make the writing and erasing transistor thereof conductive, and writing voltage applying means for applying a writing voltage to the writing and erasing word line connected to the first selected memory cell to invert a direction of a polarization of said ferroelectric gate film or retain the polarization in an initial direction, in accordance with data to be written; reading means for selecting any second selected memory cell from among the memory cells of the matrix array and reading data from the second selected memory cell, said reading means including: means for applying a second specified voltage to the reading word line connected to the second selected memory cell to make the reading transistor thereof conductive, and data detecting means for checking whether a series circuit of said reading transistor and said storing field effect transistor of the second selected memory cell is conductive or not; and erasing means for selecting any third selected memory cell from among the memory cells of the matrix array and erasing data from the third selected memory cell, said erasing means including: means for applying a third specified voltage to the bit line connected to the third selected memory cell to make the writing and erasing transistor thereof conductive, and means for applying an erasing electric field to the ferroelectric gate film contained in the storing field effect transistor of the third selected memory cell to turn the polarization of said ferroelectric gate film to a specified direction.

Claim 21

A nonvolatile semiconductor memory device, comprising: a semiconductor substrate; a plurality of memory cells aligned in rows and columns in a matrix array on said semiconductor substrate, each memory cell including: a storing field effect transistor having a ferroelectric gate film formed on said semiconductor substrate, a gate electrode formed on the ferroelectric gate film, a reading transistor connected in series to said storing field effect transistor, and a writing and erasing transistor connected to the gate electrode of said storing field effect transistor; a separate corresponding reading word line for each row of said rows, each reading word line connected to a gate of said reading transistor in each memory cell of the memory cells aligned in the row to which the reading word line corresponds; a separate corresponding writing and erasing word line for each row of said rows, each writing and erasing word line connected to said writing and erasing transistor at a side of said writing and erasing transistor opposite to said storing field effect transistor in each memory cell of the memory cells aligned in the row to which the writing and erasing word line corresponds; a separate corresponding bit line for each column of said columns, each bit line connected to said reading transistor at a side of said reading transistor opposite to said storing field effect transistor in each memory cell of the memory cells aligned in said each column; means for applying a voltage provided on any one of said bit lines, to a gate of said writing and erasing transistor of each of the memory cells aligned in the column to which the one bit line corresponds; writing means for selecting any first selected memory cell from among the memory cells of the matrix array and writing data in the first selected memory cell, said writing means including: means for applying a first specified voltage to the bit line connected to the first selected memory cell to make the writing and erasing transistor thereof conductive, and writing voltage applying means for applying a writing voltage to the writing and erasing word line connected to the first selected memory cell to invert a direction of a polarization of said ferroelectric gate film or retain the polarization in an initial direction, in accordance with data to be written; reading means for selecting any second selected memory cell from among the memory cells of the matrix array and reading data from the second selected memory cell, said reading means including: means for applying a second specified voltage to the reading word line connected to the second selected memory cell to make the reading transistor thereof conductive, and data detecting means for checking whether a series circuit of said reading transistor and said storing field effect transistor of the second selected memory cell is conductive or not; and erasing means for selecting any third selected memory cell from among the memory cells of the matrix array and erasing data from the third selected memory cell, said erasing means including: means for applying a third specified voltage to the bit line connected to the third selected memory cell to make the writing and erasing transistor thereof conductive, and means for applying an erasing electric field to the ferroelectric gate film contained in the storing field effect transistor of the third selected memory cell to turn the polarization of said ferroelectric gate film to a specified direction.

Claim 22

A nonvolatile semiconductor memory device according to claim 19, wherein said data detecting means includes means for applying a specified potential to said storing field effect transistor of said second selected memory cell from a side of said storing field effect transistor opposite to said reading transistor of said second selected memory cell, and means for detecting a variation of a potential on said bit line.

Claim 23

A nonvolatile semiconductor memory device according to claim 19, wherein said writing and erasing transistor is electrically insulated from said semiconductor substrate.

Claim 24

A nonvolatile semiconductor memory device according to claim 21, wherein said writing and erasing transistor is a thin film transistor having its channel, drain and source made by selectively applying impurities into a semiconductor thin film.

Claim 25

A nonvolatile semiconductor memory device according to claim 21, wherein said reading transistor includes an impurity region formed in the semiconductor substrate; and the channel of said thin film transistor is provided on said impurity region with an insulating film intervening between them.

Claim 26

A nonvolatile semiconductor memory device according to claim 21, wherein said erasing electric field applying means includes means for applying an erasing voltage to said writing and erasing word line connected to the third selected memory cell so that the erasing electric field is applied to said ferroelectric gate film.

Claim 27

A nonvolatile semiconductor memory device according to claim 24, wherein said erasing voltage is a voltage reverse in polarity to said writing voltage.

Claim 28

A nonvolatile semiconductor memory device according to claim 19, wherein said writing and erasing transistor is formed in said semiconductor substrate.

Claim 29

A nonvolatile semiconductor memory device according to claim 26, further comprising a separate data line for each of said columns, connected to said storing field effect transistor at a side of said storing field effect transistor opposite to said reading transistor in each of the memory cells aligned in said each column; said erasing electric field applying means including means for applying a specified potential to said writing and erasing word line connected to the third selected memory cell, and means for applying an erasing voltage to said data line connected to the third selected memory cell so that the erasing electric field is applied to said ferroelectric gate film.

Claim 30

A nonvolatile semiconductor memory device according to claim 27, wherein said erasing voltage is voltage sufficiently higher than said writing voltage.

Claim 31

A nonvolatile semiconductor memory device according to claim 19, wherein said storing field effect transistor is formed in a well made in said semiconductor substrate.

Claim 32

A nonvolatile semiconductor memory device according to claim 29, further comprising a separate data line for each column connected to said well in each of the memory cells aligned in said each column; said erasing electric field applying means including means for applying a specified potential to said data line connected to the third selected memory cell so that the erasing electric field is applied to said ferroelectric gate film.

Claim 33

A nonvolatile semiconductor memory device according to claim 30, wherein said erasing voltage is almost equal to said writing voltage.

Claim 34

A nonvolatile semiconductor memory device according to claim 30, wherein said erasing means further includes means for applying said erasing voltage to a writing and erasing word line connected to any memory cell not selected.

Claim 35

A nonvolatile semiconductor memory device according to claim 19, wherein a pair of impurity regions are formed in the semiconductor substrate, and a gate of said storing field effect transistor and a gate of said reading transistor are provided between the pair of impurity regions.

Claim 36

A nonvolatile semiconductor memory device according to claim 19, wherein said erasing means selects and erases data from the memory cells one memory cell at a time.

Claim 37

A nonvolatile semiconductor memory device according to claim 19, wherein said erasing means selects and erases data from one column of the memory cells en bloc.

Claim 38

A nonvolatile semiconductor memory device according to claim 19, wherein said erasing means selects and erases data from one row of the memory cells en bloc.

Claim 39

A nonvolatile semiconductor memory device according to claim 19, wherein said erasing means selects and erases data from all of the memory cells aligned in the matrix array en bloc.

Claim 40

A nonvolatile semiconductor memory device according to claim 19, wherein the gate of the writing and erasing transistor is connected to the drain of the reading transistor.

Claim 41

A nonvolatile semiconductor memory device according to claim 19, wherein said writing means includes means, in selecting the first selected memory cell and writing data in the first selected memory cell, for applying a fourth specified voltage to the word lines connected to the non-selected memory cells, said further specified voltage being such a voltage that the polarization direction of the ferroelectric gate film is kept unchanged; and means in selecting the first selected memory cell and writing data in the first selected memory cell, for applying to the bit lines connected to the non-selected memory cells a voltage to make the writing and erasing transistor non-conductive.

Claim 42

A nonvolatile semiconductor memory device according to claim 19, wherein said erasing means includes: means, in selecting the third selected memory cell and erasing data in the third selected memory cell, for applying a fifth specified voltage to the word lines connected to the non-selected memory cells, said fifth specified voltage being such a voltage that the polarization direction of the ferroelectric gate film is kept unchanged; and means, in selecting the third selected memory cell and erasing data in the third selected memory cell, for applying to the bit line connected to the non-selected memory cell a voltage to make the writing and erasing transistor non-conductive.

Claim 43

A nonvolatile memory device according to claim 19, wherein the initial direction is the specified direction and said writing voltage applying means applies the writing voltage to the writing and erasing word line connected to the first selected memory cell to retain the polarization in the specified direction or invert the direction of polarization of said ferroelectric gate film, in accordance with the data to be written.

Claim 44

A nonvolatile memory device according to claim 41, wherein the writing voltage to invert the direction of polarization is opposite in polarity to the erasing voltage, and the writing voltage to retain the polarization in the specified direction is intermediate of the writing voltage to invert the direction of polarization and the erasing voltage.

Claim 45

A nonvolatile memory device according to claim 42, wherein the writing voltage to retain the polarization in the specified direction is a ground potential.

Claim 48

A method according to claim 44, wherein said writing and erasing transistor is electrically insulated from said semiconductor substrate, and in selecting any memory cell and erasing data in the selected memory cell, an erasing voltage is applied to said writing and erasing word line connected to the selected memory cell to turn the polarization of said ferroelectric gate film to the specified direction.

Claim 49

A method according to claim 45, wherein said erasing voltage is a voltage reverse in polarity to said writing voltage.

Claim 50

A method according to claim 44, wherein said writing and erasing transistor is formed in said semiconductor substrate; said semiconductor memory device further includes a separate corresponding data line for each column of said columns connected to said storing field effect transistor at the side of the storing field effect transistor opposite to said reading transistor in each of the memory cells aligned in said each column; and in selecting any memory cell and erasing data from the memory cell, a specified potential is applied to said writing and erasing word line connected to the selected memory cell, and an erasing voltage is applied to said data line connected to the selected memory cell to turn the polarization of said ferroelectric gate film to the specified direction.

Claim 51

A method according to claim 47, wherein said erasing voltage is a voltage sufficiently higher than said writing voltage.

Claim 52

A method according to claim 44, wherein said storing field effect transistor is formed in a well formed in said semiconductor substrate; said semiconductor memory device further includes a separate corresponding data line for each of the columns connected to said well in each of the memory cells aligned in the column; and in selecting any memory cell and erasing data in the selected memory cell, a specified potential is applied to said writing and erasing word line connected to the selected memory cell, and an erasing voltage is applied to said data line connected to the selected memory cell to turn the polarization of the ferroelectric gate film to the specified direction.

Claim 53

A method according to claim 49, wherein said erasing voltage is almost equal to said writing voltage.

Claim 54

A method according to claim 49, wherein in selecting any memory cell and erasing data in the selected memory cell, said erasing voltage is applied to a writing and erasing word line connected to any memory cell not selected.

Claim 55

A method according to claim 44, wherein in erasing data, only one of the memory cells is selected at a time.

Claim 56

A method according to claim 44, wherein in erasing data, the memory cells aligned in the column direction are selected en bloc.

Claim 57

A method according to claim 44, wherein in erasing data, the memory cells aligned in the row direction are selected en bloc.

Claim 58

A method according to claim 44, wherein in erasing data, the memory cells aligned in a matrix manner are all selected en bloc.

Claim 59

A method according to claim 44, further comprising the steps of: in selecting any memory cell and writing data in the selected memory cell, applying a fourth specified voltage to the word lines connected to the non-selected memory cells, said first specified voltage being such voltage that the polarization direction of the ferroelectric gate film is kept uncharged; and in selecting any memory cell and writing data in the selected memory cell, applying to the bit line connected to the non-selected memory cell a voltage to make the writing and erasing transistor non-conductive.

Claim 60

A method according to claim 44, further comprising the steps of: in selecting any memory cell and erasing data in the selected memory cell, applying a fifth specified voltage to the word lines connected to the non-selected memory cells, said fifth specified voltage being such a voltage that the polarization direction of the ferroelectric gate film is kept unchanged; and in selecting any memory cell and erasing data in the selected memory cell, applying to the bit line connected to the non-selected memory cell a voltage to make the writing and erasing transistor non-conductive.

Claim 61

A method according to claim 44, wherein the initial direction of polarization is the specified direction, so that in selecting any memory cell and writing data in the selected memory cell, the writing voltage is applied to the writing and erasing word line connected to the selected memory cell so as to retain the polarization of said ferroelectric gate film in the specified direction or invert the direction of polarization, in accordance with the data to be written.

Claim 64

A method according to claim 59, wherein the writing voltage to invert the direction of polarization is opposite in polarity to the erasing voltage, and the writing voltage to retain the polarization in the specified direction is intermediate of the writing voltage to invert the direction of polarization and the erasing voltage.

Claim 65

A method according to claim 60, wherein the writing voltage to retain the polarization in the specified direction is a ground potential.