System for interconnecting VLSI circuits with transmission line characteristics

Claim 3

A system as in claim 1, wherein said output buffers include an output buffer having a variable output impedance.

Claim 4

A system as in claim 1, wherein said transmission line is connected end-to-end to form a closed loop.

Claim 5

A system as in claim 1, wherein said plurality of input buffers and said plurality of output buffers are equal in number, and wherein each such input buffers is associated with a corresponding one of said output buffers to form a transceiver.

Claim 6

A system as in claim 4, wherein said transmission line is connected end-to-end to form a closed loop, and wherein said transceivers are spaced on said closed-loop transmission line in roughly equal intervals.

Claim 7

A system as in claim 1, further comprising means connected to said output buffer for limiting an output signal from said output buffer to first and second intermediate voltage levels each having a value between a supply voltage and a ground voltage, said first and second intermediate voltage levels being selected as the terminating voltages of said terminating resistances.

Claim 8

A system as in claim 6, wherein the difference between said first and second intermediate voltage levels is in excess of the voltage swing of said output buffer.

Claim 9

A system as in claim 1, wherein said input buffer has an impedance which is higher during said initial phase of said clock signal than during a time period subsequent to said initial phase of said clock signal.

Claim 10

A system as in claim 8, wherein said impedance is variable only during a clock period of said clock signal when said input signal to said input buffer changes state.

Claim 11

A system as in claim 1, wherein one or more of said input buffers include means for achieving said active input impedances comprising feedback impedances and a control circuit for disabling said feedback impedances individually.

Claim 12

A system as in claim 10, wherein said means for achieving active input impedances further comprises means responsive to said input signal for detecting a logic state transition in said input signal, and for enabling said control circuit in response to said logic state transition detected.

Claim 13

A system as in claim 10, wherein said feedback impedances each comprise an inverter sized to provide a desired impedance.

Claim 14

A system as in claim 11, further comprising means for delaying said input signal by said initial phase of said clock signal, said initial phase of said clock signal being approximately one half of a period of said clock signal.

Claim 15

A system as in claim 13, wherein said means for delaying said input signal comprises two latches clocked by opposite phase of said clock signal.

Claim 16

A system as in claim 10, wherein one or more of said input buffers each associate with a corresponding one of said output buffers to form a transceiver, and wherein said feedback impedances in said one or more input buffers are provided in said corresponding one of said output buffers.

Claim 17

A system as in claim 15, wherein said output buffer of said transceivers each comprise: a first buffer for providing an output signal; a second buffer sized for providing a desired feedback impedance; and an enabling circuit receiving one or more control signals from said control circuit, said enabling circuit enabling said first and second buffers when said transceiver is designated for providing said output signal, and enabling said second buffer when said transceiver is designated for providing said desired feedback impedance.

Claim 18

A system as in claim 6, wherein the difference between said first and second intermediate voltages is less than the output voltage swing of said output buffer, and said system further comprising means for disabling said output buffer prior to a new cycle of said clock signal, so as to allow said transmission line to attain one of said terminating voltages.

Claim 19

A system as in claim 1, wherein said input buffer comprises an impedance to provide input hysteresis.

Claim 20

A variable impedance input buffer receiving an input signal, said input signal having first and second logic states, comprising: an input buffer receiving said input signal for providing an output signal; first means coupled to said input buffer for coupling said input signal to a first supply voltage when said input signal is in said first logic state, said first means for coupling providing said input signal a first impedance path to said first supply voltage during said initial phase of said clock signal, and providing said input signal a second impedance path to said first supply voltage after said initial phase of said clock signal, said first impedance path to said first supply voltage having an impedance larger than said second impedance path to said first supply voltage; and second means coupled to said input signal for coupling said input signal to a second supply voltage when said input signal is in said second logic state, said second means for coupling providing said input signal a first impedance path to said second supply voltage during said initial phase of said clock signal, and providing said input signal a second impedance path to said second supply voltage after said initial phase of said clock signal, said first impedance path to said second supply voltage having an impedance larger than said second impedance path to said second supply voltage.

Claim 21

A variable impedance input buffer receiving an input signal, said input signal having first and second logic states, comprising: an input buffer receiving said input signal for providing an output signal; first means coupled to said input buffer for coupling said input signal to a first supply voltage when said input signal is in said first logic state, said first means for coupling providing said input signal a first impedance path to said first supply voltage during said initial phase of said clock signal, and providing said input signal a second impedance path to said first supply voltage after said initial phase of said clock signal, said first impedance path to said first supply voltage having an impedance larger than said second impedance path to said first supply voltage; and second means coupled to said input signal for coupling said input signal to a second supply voltage when said input signal is in said second logic state, said second means for coupling providing said input signal a first impedance path to said second supply voltage during said initial phase of said clock signal, and providing said input signal a second impedance path to said second supply voltage after said initial phase of said clock signal, said first impedance path to said second supply voltage having an impedance larger than said second impedance path to said second supply voltage.

Claim 22

A variable impedance input buffer as in claim 19, wherein first and second impedance paths to each supply voltage comprise respectively first and second transistors sized such that the on-impedance of said first transistor exceeds the on-impedance of said second transistor.

Claim 23

A variable impedance output buffer receiving an input signal and providing an output signal, comprising: an output buffer receiving said input signal to provide said output signal at an output terminal, said output buffer including means responsive to one or more gain adjustment signals for adjusting the gain of said output buffer; and means receiving said output signal for providing said one or more gain adjustment signals, said means for providing said gain adjustment signal provides said gain adjustment signals in a manner such that said gain of said output buffer decreases until a predetermined minimum gain is reached, and maintaining said gain of said output buffer thereafter so as to maintain said output signal at a predetermined voltage level.

Claim 24

A variable impedance output buffer receiving an input signal and providing an output signal, comprising: an output buffer receiving said input signal to provide said output signal at an output terminal, said output buffer including means responsive to one or more gain adjustment signals for adjusting the gain of said output buffer; and means receiving said output signal for providing said one or more gain adjustment signals, said means for providing said gain adjustment signal provides said gain adjustment signals in a manner such that said gain of said output buffer decreases until a predetermined minimum gain is reached, and maintaining said gain of said output buffer thereafter so as to maintain said output signal at a predetermined voltage level.

Claim 25

A variable impedance output buffer as in claim 21, wherein said means for adjusting the gain of said output buffer comprises: a plurality of parallel transistors each providing a corresponding predetermined impedance between said output terminal and a supply voltage source; and means receiving said one or more gain adjustment signals for enabling selected ones of said plurality of parallel transistors in accordance with said gain adjustment signals.

Claim 26

A variable impedance output buffer as in claim 22, wherein said means for enabling selected ones of said plurality of parallel transistorsincludes means for discharging a transistor through a drain terminal of said transistor, said drain terminal of said transistor being coupled to said output terminal.

Claim 27

A variable impedance output buffer as in claim 23, wherein said means for discharging a transistor connects a gate of said transistor to said drain terminal of said transistor through a diode-connected transistor.

Claim 28

A variable impedance output buffer as in claim 22, wherein said means for providing said one or more gain adjustment signals provides said gain adjustment signals such that said plurality of parallel transistor are enabled in a predetermined sequence.

Claim 31

A method as in claim 26, wherein said step of providing a plurality of output buffers provides an output buffer having a variable output impedance.

Claim 32

A method as in claim 26, wherein said step of providing a transmission line connects said transmission line end-to-end to form a closed loop.

Claim 33

A method as in claim 26, wherein said steps of providing a plurality of input buffers and a plurality of output buffers provides equal number of input and output buffers, and wherein each such input buffers is associated with a corresponding one of said output buffers to form a transceiver.

Claim 34

A method as in claim 29, wherein said step of providing a transmission line is connected end-to-end to form a closed loop, and wherein said transceivers are spaced on said closed-loop transmission line in roughly equal intervals.

Claim 35

A method as in claim 26, further comprising the step of connecting said output buffer so as to limit an output signal from said output buffer to first and second intermediate voltage levels each having a value between a supply voltage and a ground voltage, said first and second intermediate voltage levels being selected as the terminating voltages of said terminating resistances.

Claim 36

A method as in claim 31, wherein the difference between said first and second intermediate voltage levels is in excess of the voltage swing of said output buffer.

Claim 37

A method as in claim 26, wherein said input buffer has an impedance which is higher during said initial phase of said clock signal than during a time period subsequent to said initial phase of said clock signal.

Claim 38

A method as in claim 33, wherein said impedance is variable only during a clock period of said clock signal when said input signal to said input buffer changes state.

Claim 39

A method as in claim 26, wherein said step of providing input buffers achieves said active input impedances by including the step of providing feedback impedances and the step of providing a control circuit for disabling said feedback impedances individually.

Claim 40

A method as in claim 35, further comprising the step of detecting in response to said input signal a logic state transition in said input signal, said logic state transition detected enabling said control circuit.

Claim 41

A method as in claim 35, wherein said step of providing feedback impedances provides for each feedback impedance an inverter sized to provide a desired impedance.

Claim 42

A method as in claim 36, further comprising the step of delaying said input signal by said initial phase of said clock signal, said initial phase of said clock signal being approximately one half of a period of said clock signal.

Claim 43

A method as in claim 38, wherein said step of delaying said input signal provides two latches clocked by opposite phase of said clock signal.

Claim 44

A method as in claim 35, wherein said step of providing said input buffers provides one or more input buffers each associated with a corresponding one of said output buffers to form a transceiver, and wherein said feedback impedances in said one or more input buffers are provided in said corresponding one of said output buffers.

Claim 45

A method as in claim 40, wherein said output buffer of said transceivers are each provided by a second method comprising the steps of: providing a first buffer to generate an output signal; providing a second buffer sized to have a desired feedback impedance; and providing an enabling circuit receiving one or more control signals from said control circuit, said enabling circuit enabling said first and second buffers when said transceiver is designated for providing said output signal, and enabling said second buffer when said transceiver is designated for providing said desired feedback impedance.

Claim 46

A method as in claim 31, wherein the difference between said first and second intermediate voltages is less than the output voltage swing of said output buffer, and said method further comprising the step of disabling said output buffer prior to a new cycle of said clock signal, so as to allow said transmission line to attain one of said terminating voltages.

Claim 47

A method as in claim 26, wherein said input buffer is provided an impedance to effectuate input hysteresis.

Claim 50

A method as in claim 44, wherein steps of providing said input signal first and second impedance paths to each supply voltage comprise respectively the steps of providing first and second transistors sized such that the on-impedance of said first transistor exceeds the on-impedance of said second transistor.