Patent EP0237321A2 successfully refreshed from Google Patents.
US5349671A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor system generating instruction fetch addresses at high speed
Assignee: Panasonic Holdings Corp
•
Filing: 1990-03-16
•
Granted: 1994-09-20
•
Expires: 2010-03-16
Abstract
Abstract A microprocessor system which comprises an arithmetic logic unit for generating flags, a flag update detector for outputting a flag update detecting signal, a status register coupled to the flag update detector and the arithmetic logic unit for receiving the flag update detecting signal and a flag outputted from the arithmetic logic unit, a first address outputting portion coupled to the flag update detector and the status register for receiving the flag update detecting signal, a flag outputted from the status register, a target instruction address, a next instruction address and a branch condition for determining according to the flag received from the status register whether or not the branch condition is met, and for outputting first and second address candidates selected from the target instruction address and the next instruction address according to the flag update signal and to whether or not the branch condition is met, and a second address outputting portion coupled to the first address outputting portion and the arithmetic logic unit for receiving the first and second address candidates outputted from the first address outputting portion, the branch condition and the flag outputted from the arithmetic logic unit, for determining according to the flag received from the arithmetic logic unit whether or not the branch condition is met, and for outputting the target instruction address or the next instruction address as an instruction fetch address on the basis of a result of determining according to the flag received from the arithmetic logic unit whether or not the branch condition is met.
Inventors
- 👤 Toshinori Maeda
- 👤 Tomoharu Kawada
- 👤 Jiro Miyake
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:23
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30094; G06F9/30003; G06F9/3005; G06F9/30058; G06F9/30072
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
265 words
A microprocessor system comprising: an arithmetic logic unit for generating flats; a flag update detector for outputting a flag update detecting signal; a status register coupled to said flag update detector and said arithmetic logic unit for receiving the flag update detecting signal and a flag outputted from said arithmetic logic unit; a first address outputting portion coupled to said flag update detector and said status register for receiving the flag update detecting signal, a flag outputted from said status register, a target instruction address, a next instruction address and a branch condition of a conditional branch instruction, for determining according to the flag received from said status register whether or not the branch condition is met, and for outputting first and second address candidates selected from the target instruction address and the next instruction address according to the flag update signal and to whether or not the branch condition is met; and a second address outputting portion coupled to said first address outputting portion and said arithmetic logic unit for receiving the first and second address candidates outputted from said first address outputting portion, the branch condition of the conditional branch instruction and the flag outputted from said arithmetic logic unit, for determining according to the flag received from said arithmetic logic unit whether or not the branch condition is met, and for outputting the target instruction address or the next instruction address as an instruction fetch address on the basis of a result of determining according to the flag received from said arithmetic logic unit whether or not the branch condition is met.
Claim 2
Dependent Claim
265 words
A microprocessor system comprising: an arithmetic logic unit for generating flats; a flag update detector for outputting a flag update detecting signal; a status register coupled to said flag update detector and said arithmetic logic unit for receiving the flag update detecting signal and a flag outputted from said arithmetic logic unit; a first address outputting portion coupled to said flag update detector and said status register for receiving the flag update detecting signal, a flag outputted from said status register, a target instruction address, a next instruction address and a branch condition of a conditional branch instruction, for determining according to the flag received from said status register whether or not the branch condition is met, and for outputting first and second address candidates selected from the target instruction address and the next instruction address according to the flag update signal and to whether or not the branch condition is met; and a second address outputting portion coupled to said first address outputting portion and said arithmetic logic unit for receiving the first and second address candidates outputted from said first address outputting portion, the branch condition of the conditional branch instruction and the flag outputted from said arithmetic logic unit, for determining according to the flag received from said arithmetic logic unit whether or not the branch condition is met, and for outputting the target instruction address or the next instruction address as an instruction fetch address on the basis of a result of determining according to the flag received from said arithmetic logic unit whether or not the branch condition is met.
Claim 3
Dependent Claim
82 words
A microprocessor system as set forth in claim 1, wherein said first address outputting portion comprises: a first predicate evaluation circuit for receiving the flag outputted from said status register; and a first address selecting circuit for receiving the target instruction address and the next instruction address and outputting a first and second address candidates in accordance with a branch taking notice signal outputted from said first predicate evaluation circuit and a flag update detecting signal outputted from a flag update detector.
Claim 4
Dependent Claim
83 words
A microprocessor system as set forth in claim 2, wherein said second address outputting portion comprises: a second predicate evaluation circuit for receiving the flag outputted from said arithmetic logical unit; and a second address selecting circuit for receiving the first and second address candidates outputted from said first address selecting circuit and outputting the target instruction address and the next instruction address as an instruction fetch address in accordance with a branch taking notice signal outputted from said second predicate evaluation circuit.
Claim 5
Dependent Claim
133 words
A microprocessor system as set forth in claim 2, wherein the target instruction address is outputted as the first address candidate and on the other hand the next instruction address is outputted as the second address candidate in case where the flag update detecting signal outputted from said flag update detector to said first address outputting portion is asserted, wherein the target instruction address is outputted as the first and second address candidates in case where the flag update detecting signal is negated and the branch taking notice signal indicates that a branch is taken, and wherein the next instruction address is outputted as the first and second address candidates in case where the flag update detecting signal is negated and the branch taking notice signal indicates that a branch is not taken.
Claim 6
Dependent Claim
132 words
A microprocessor system as set forth in claim 3, wherein a flag generating means of said arithmetic logical unit generates a carry flag, a zero flag, a negative flag, an overflow flag and a flag, which has a logical value equal to an exclusive-OR of the negative and overflow flags by using values represented by the most significant bits of two input data of said arithmetic logical unit and a value indicated by the most significant bit of the result of an arithmetic operation performed by said arithmetic logical unit, in parallel with each other and inputs the carry flag, the zero flag, the negative flag, the overflow flag and the flag having the logical value equal to the exclusive-OR of the negative and overflow flags into said second predicate evaluation circuit.
Claim 7
Dependent Claim
327 words
A microprocessor system as set forth in claim 1, wherein a flag generating means of said arithmetic logical unit, which is of a carry selecting type having a lower order arithmetic logical unit and a pair of a first and second upper order arithmetic logical units, comprises: a flag generating circuit for generating from an output of each of said first and second upper order arithmetic logical units a carry flag, a zero flag, a negative flag, an overflow flag and a flag, which has a logical value equal to an exclusive-OR of the negative and overflow flags, by using a value indicated by the most significant bit of the two input data to said arithmetic logical unit and values indicated by the most significant bits of the results of the arithmetic operations performed in said first and second upper order arithmetic units, and for outputting the carry flag, the zero flag, the negative flag, the overflow flag and the flag having the logical value equal to the exclusive-OR of the negative and overflow flags corresponding to each of said pair of said first and second upper order arithmetic logical units; and a group of selectors for receiving the pair of groups of the carry flags, the zero flags, the negative flags, the overflow flags and the flags each having the logical value equal to the exclusive-OR of the negative and overflow flags outputted from said flag generating circuit and a carry outputted from said lower order arithmetic unit, choosing one of the pair of groups of the carry flags, the zero flags, the negative flags, the overflow flags and the flags each having the logical value equal to the exclusive-OR of the negative and overflow flags outputted from said flag generating circuit and outputting the chosen carry flag, zero flag, negative flag, overflow flag and the flag having the logical value equal to the exclusive-OR of the negative and overflow flags to said predicate evaluation circuit.
Claim 8
Dependent Claim
129 words
A microprocessor system as set forth in claim 5, wherein the generation of the flag having the logical value X equal to the exclusive-OR of the negative and overflow flows is performed by using a first value a represented by the most significant bit of one of the two input data to said arithmetic logical unit and a second value b represented by the most significant bit of the other input data to said arithmetic logical unit and a third value r represented by the most significant bit of the result of the arithmetic operation performed on the two input data which satisfy one of the following logical expressions: (a) in case where the arithmetic operation is addition, X=(a+b)·r+a·b·r (b) in case where the arithmetic operation is subtraction, X=(a+b)·r+a·b·r.
Claim 9
Dependent Claim
142 words
A microprocessor system as set forth in claim 6, wherein the generation of the flag having the logical value X equal to the exclusive-OR of the negative and overflow flags is performed in said flag generating circuit by using a first value a represented by the most significant bit of one of the two input data to each of said upper order arithmetic logical units and a second value b represented by the most significant bit of the other input data to each of said upper order arithmetic logical units and a third value r represented by the most significant bit of the result of the arithmetic operation performed on the two input data which satisfy one of the following logical expressions: (a) in case where the arithmetic operation is addition, X=(a+b)·r+a·b·r (b) in case where the arithmetic operation is subtraction, X=(a+b)·r+a·b·r.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-19 | 1998-03-21 | 1998-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-19 | 2002-03-21 | 2002-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-19 | 2006-03-21 | 2006-09-20 | $7700.00 | Window Closed / Lapsed |