US5351015A
Expired / Lapsed
US
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Time based data separator zone change sequence
Assignee: SSI
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Filing: 1993-02-03
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Granted: 1994-09-27
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Expires: 2013-02-03
Abstract
Abstract The present invention provides a method and an apparatus for controlling initial transients in a frequency synthesizer by controlling the start-up sequence of the device. The start-up sequence comprises several steps. The voltage controlled oscillator(s) (VCO) is reset so that the VCO(s) are in a known state during start-up. The charge pump and phase detector of phase-locked loop (PLL) are disabled. New data values are loaded into counter(s)/register(s) that control the frequency of the VCO(s). Also, a data value is provided to a digital-to-analog converter (DAC) to set the data rate for the PLL. A fixed amount of time is provided as a delay for the DAC to settle (i.e., 1.6 μs). Divide-by-M and divide-by-N counters are then enabled. Also, the phase detector of the phase-locked loop (PLL) is enabled. The VCO is then restarted. By utilizing a start-up sequence, the center frequency of the VCO is already settled when changing frequencies, the divide-by-M and divide-by-N counters are matched, the VCO starts in phase with the reference frequency of the reference signal, and the voltage of the loop filter is prevented from railing. By using dual buffered registers for each counter, loading of the divide-by-M and divide-by-N counters is accomplished without shutting down the VCO. A timer provides a 1.6 μs delay to allow the DAC to settle. Digital logic is used to synchronize signals. Delay compensation circuitry is used to implement delay cancellation for zero phase restart.
Inventors
- 👤 Rodney T. Masumoto
- 👤 Shunsaku Ueda
- 👤 Jenn-Gang Chern
- 👤 Kirby Lam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 23:34
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; H; H03; H03L; H03L3/00; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891; H03L7/16; H03L7/18; H03L7/183; H03L7/187; H03L7/189; G11B20/12; G11B20/1217; G11B20/1258; H03L2207/00; H03L2207/06
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
141 words
A method for reducing transients in a frequency synthesizer circuit by controlling the startup sequence comprising the steps of: loading an initial data value into a digital-to-analog converting means, said digital-to-analog converting means being coupled to a phase comparison means, an amplification means and a voltage controlled oscillator means; loading new data values into a first and second register means of a corresponding first and second counting means, respectively, said first and second counting means being coupled to said phase comparison means; resetting said voltage controlled oscillator means to a predetermined state wherein said oscillating means is coupled to said second counting means; disabling said phase comparing means; pausing for a predetermined period of time for said digital-to-analog converting means to stabilize; reactuating said first and second counting means; and restarting said phase comparing means and said voltage controlled oscillator means.
Claim 2
Independent Claim
141 words
A method for reducing transients in a frequency synthesizer circuit by controlling the startup sequence comprising the steps of: loading an initial data value into a digital-to-analog converting means, said digital-to-analog converting means being coupled to a phase comparison means, an amplification means and a voltage controlled oscillator means; loading new data values into a first and second register means of a corresponding first and second counting means, respectively, said first and second counting means being coupled to said phase comparison means; resetting said voltage controlled oscillator means to a predetermined state wherein said oscillating means is coupled to said second counting means; disabling said phase comparing means; pausing for a predetermined period of time for said digital-to-analog converting means to stabilize; reactuating said first and second counting means; and restarting said phase comparing means and said voltage controlled oscillator means.
Claim 3
Independent Claim
101 words
A method for starting up a frequency synthesizer circuit, said circuit comprising a phase comparison means coupled to a voltage controlled oscillator (VCO) and to a digital-to-analog converter (D/A), the method comprising the steps of: loading said D/A with a predetermined data value, then pausing for a predetermined period of time for said D/A to stabilize; disabling said phase comparison means and said VCO for said predetermined period of time; and enabling said phase comparison means and said VCO when said predetermined period of time has elapsed, whereby said VCO begins to synthesize a frequency corresponding to said predetermined data value.
Claim 4
Independent Claim
101 words
A method for starting up a frequency synthesizer circuit, said circuit comprising a phase comparison means coupled to a voltage controlled oscillator (VCO) and to a digital-to-analog converter (D/A), the method comprising the steps of: loading said D/A with a predetermined data value, then pausing for a predetermined period of time for said D/A to stabilize; disabling said phase comparison means and said VCO for said predetermined period of time; and enabling said phase comparison means and said VCO when said predetermined period of time has elapsed, whereby said VCO begins to synthesize a frequency corresponding to said predetermined data value.
Claim 5
Dependent Claim
18 words
The method of claim 2 wherein said predetermined data value represents a particular zone of a data disk.
Claim 6
Dependent Claim
20 words
The method of claim 3 wherein said synthesized frequency increases in response to an increase in said predetermined data value.
Claim 7
Dependent Claim
25 words
The method of claim 3 wherein said phase comparison means is comprised of a phase detector, a charge pump, a loop filter, and an amplifier.
Claim 8
Dependent Claim
15 words
The method of claim 2 wherein said predetermined period of time is approximately 1.6 microseconds.
Claim 9
Dependent Claim
83 words
A start-up circuit for a frequency synthesizer, said frequency synthesizer comprising a phase comparison means coupled to a voltage controlled oscillator (VCO), and a digital-to-analog converter (D/A) coupled to said phase comparison means and said VCO, the start-up circuit comprising: means for timing a period of time elapsed after loading said D/A with a predetermined data value; and means coupled to and driven by said timing means for enabling said phase comparison means and said VCO when said period of time has elapsed.
Claim 10
Dependent Claim
83 words
A start-up circuit for a frequency synthesizer, said frequency synthesizer comprising a phase comparison means coupled to a voltage controlled oscillator (VCO), and a digital-to-analog converter (D/A) coupled to said phase comparison means and said VCO, the start-up circuit comprising: means for timing a period of time elapsed after loading said D/A with a predetermined data value; and means coupled to and driven by said timing means for enabling said phase comparison means and said VCO when said period of time has elapsed.
Claim 11
Dependent Claim
15 words
The start-up circuit of claim 7 wherein the timing means is comprised of a timer.
Claim 12
Dependent Claim
31 words
The start-up circuit of claim 7 wherein said start-up circuit includes means for disabling said phase comparison means and said VCO when said D/A is loaded with said predetermined data value.
Claim 13
Dependent Claim
44 words
The start-up circuit of claim 7 wherein said enabling means is comprised of a restart sequencer coupled to an input reference signal and said timing means, said restart sequencer enabling said phase comparison means and said VCO when said period of time has elapsed.
Claim 14
Dependent Claim
44 words
The start-up circuit of claim 10 further comprising means for setting said ratio of a frequency of said input reference signal to a frequency of an output of said frequency synthesizer, said ratio setting means being coupled to and driven by said restart sequencer.
Claim 15
Dependent Claim
53 words
The start-up circuit of claim 11 wherein said ratio setting means is comprised of a divide by N counter and a divide by M counter, wherein said ratio of N to M controls said ratio of said frequency of said input reference signal to said frequency of said output of said frequency synthesizer.
Claim 16
Dependent Claim
28 words
The start-up circuit of claim 11 wherein said restart sequencer enables said ratio setting means substantially concurrently with said loading of said D/A with said predetermined data value.
Claim 17
Dependent Claim
31 words
The start-up circuit of claim 11 further comprising a delay compensation circuit for setting to zero said phase difference between said output of said frequency synthesizer and said input reference signal.
Claim 18
Dependent Claim
26 words
The start-up circuit of claim 7 wherein said phase comparison means is comprised of a phase detector, a charge pump, a loop filter, and an amplifier.
Claim 19
Dependent Claim
84 words
A start-up circuit for a frequency synthesizer, said frequency synthesizer comprising a phase comparison means coupled to a voltage controlled oscillator (VCO), and a digital-to-analog converter (D/A) coupled to said phase comparison means and said VCO, the start-up circuit comprising: a timer for timing a period of time elapsed after loading said D/A with a predetermined data value; and an enabler coupled to and driven by said timer for enabling said phase comparison means and said VCO when said period of time has elapsed.
Claim 20
Dependent Claim
84 words
A start-up circuit for a frequency synthesizer, said frequency synthesizer comprising a phase comparison means coupled to a voltage controlled oscillator (VCO), and a digital-to-analog converter (D/A) coupled to said phase comparison means and said VCO, the start-up circuit comprising: a timer for timing a period of time elapsed after loading said D/A with a predetermined data value; and an enabler coupled to and driven by said timer for enabling said phase comparison means and said VCO when said period of time has elapsed.
Claim 21
Dependent Claim
32 words
The start-up circuit of claim 16 wherein said start-up circuit includes a disabler for disabling said phase comparison means and said VCO when said D/A is loaded with said predetermined data value.
Claim 22
Dependent Claim
42 words
The start-up circuit of claim 16 wherein said enabler is comprised of a restart sequencer coupled to an input reference signal and said timer, said restart sequencer enabling said phase comparison means and said VCO when said period of time has elapsed.
Claim 23
Dependent Claim
136 words
A frequency synthesizer for generating a frequency corresponding to a particular zone of a data disk, said frequency synthesizer comprising: a voltage controlled oscillator (VCO); a phase comparison means coupled to and driving said VCO; a digital-to-analog converting means (D/A) coupled to and controlling said VCO and said phase comparison means; and a start-up circuit driven by an input reference signal, said start-up circuit being coupled to said VCO and said phase comparison means, wherein said start-up circuit disables said VCO and said phase comparison means when said D/A is loaded with a predetermined data value, and wherein said start-up circuit enables said VCO and said phase comparison means when a period of time has elapsed after said D/A is loaded with said predetermined data value, said start-up circuit thereby reducing transients in said frequency synthesizer.
Claim 24
Dependent Claim
136 words
A frequency synthesizer for generating a frequency corresponding to a particular zone of a data disk, said frequency synthesizer comprising: a voltage controlled oscillator (VCO); a phase comparison means coupled to and driving said VCO; a digital-to-analog converting means (D/A) coupled to and controlling said VCO and said phase comparison means; and a start-up circuit driven by an input reference signal, said start-up circuit being coupled to said VCO and said phase comparison means, wherein said start-up circuit disables said VCO and said phase comparison means when said D/A is loaded with a predetermined data value, and wherein said start-up circuit enables said VCO and said phase comparison means when a period of time has elapsed after said D/A is loaded with said predetermined data value, said start-up circuit thereby reducing transients in said frequency synthesizer.
Claim 25
Dependent Claim
57 words
The frequency synthesizer of claim 19 wherein said start-up circuit is comprised of: means for timing said period of time elapsed after said D/A is loaded with said predetermined data value; and means coupled to and driven by said timing means for enabling said phase comparison means and said VCO when said period of time has elapsed.
Claim 26
Dependent Claim
58 words
The frequency synthesizer of claim 19 wherein said start-up circuit is comprised of: a timer for timing said period of time elapsed after said D/A is loaded with said predetermined data value; and an enabler coupled to and driven by said timer for enabling said phase comparison means and said VCO when said period of time has elapsed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-26 | 1998-03-28 | 1998-09-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-26 | 2002-03-28 | 2002-09-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-26 | 2006-03-28 | 2006-09-27 | $7700.00 | Window Closed / Lapsed |