Driving device and display system

Claim 2

A driving device, comprising: matrix electrodes composed of scanning lines and information lines; an information line driving circuit having a delay circuit for delaying the transfer of image information corresponding to writing into pixels of a scanning line, a serial-parallel converting circuit, and a first memory for storing the image information from said serial-parallel converting circuit; a scanning line driving circuit having a scanning line designating circuit for generating scanning line information which designates a scanning line, and a second memory for storing the scanning line information generated by said scanning line designating circuit; and control means for controlling said information line driving circuit and said scanning line designating circuit so that the image information stored in said first memory which is used for Nth scanning, the scanning line information from said scanning line designating circuit which is used to designate a scanning line for (N+1)th scanning, and the scanning line information stored in said second memory which is used to designate a scanning line for Nth scanning are synchronously output, and said scanning line information used to designate the scanning line for (N+1)th scanning is output during outputting of the scanning line information for Nth scanning, and pixels on the scanning line designated by the scanning line information used to designate the scanning line for (N+1)th scanning are erased, and pixels on the scanning line designated by said scanning line information for designating Nth scanning stored in said second memory are written according to said image information stored in said first memory used for Nth scanning.

Claim 3

A driving device, comprising: matrix electrodes composed of scanning lines and information lines; an information line driving circuit having a delay circuit for delaying the transfer of image information corresponding to writing into pixels of a scanning line, a serial-parallel converting circuit, and a first memory for storing the image information from said serial-parallel converting circuit; a scanning line driving circuit having a scanning line designating circuit for designating a scanning line, and a second memory for storing the scanning line information from said scanning line designating circuit; and control means for controlling said information line driving circuit and said scanning line driving circuit so that the image information stored in said first memory which is used for Nth scanning, the scanning line information from said scanning line designating circuit which is used to designate a scanning line for (N+1)th scanning, and the scanning line information stored in said second memory which is used to designate a scanning line for Nth scanning are synchronously output, and said scanning line information used to designate the scanning line for (N+1)th scanning is output during outputting of the scanning line information for Nth scanning, and pixels on the scanning line designated by the scanning line information used to designate the scanning line for (N+1)th scanning are erased, and pixels on the scanning line designated by the scanning line information for designating Nth scanning stored in said second memory are written according to said image information stored in said first memory used for Nth scanning and, further controlling said information line driving circuit and said scanning line driving circuit, when the number of designations of the scanning lines reaches a predetermined value, so as to prohibit the transfer of image information to said delay circuit, and during the application of the writing voltage signals to the pixels of the scanning line designated according to the information from said second memory, to apply a non-selection signal to the other scanning lines.

Claim 4

A driving device, comprising: matrix electrodes composed of scanning lines and information lines; an information line driving circuit having a delay circuit for delaying the transfer of image information corresponding to writing into pixels of a scanning line, a serial-parallel converting circuit, and a first memory for storing the image information from said serial-parallel converting circuit; a scanning line driving circuit having a scanning line designating circuit for designating a scanning line, and a second memory for storing the scanning line information from said scanning line designating circuit; and control means for controlling said information line driving circuit and said scanning line driving circuit so that the image information stored in said first memory which is used for Nth scanning, the scanning line information from said scanning line designating circuit which is used to designate a scanning line for (N+1)th scanning, and the scanning line information stored in said second memory which is used to designate a scanning line for Nth scanning are synchronously output, and said scanning line information used to designate the scanning line for (N+1)th scanning is output during outputting of the scanning line information for Nth scanning, and pixels on the scanning line designated by the scanning line information used to designate the scanning line for (N+1)th scanning are erased, and pixels on the scanning line designated by the scanning line information for designating Nth scanning stored in said second memory are written according to said image information stored in said first memory used for Nth scanning and, further controlling said information line driving circuit and said scanning line driving circuit, when the number of designations of the scanning lines reaches a predetermined value, so as to prohibit the transfer of image information to said delay circuit, and during the application of the writing voltage signals to the pixels of the scanning line designated according to the information from said second memory, to apply a non-selection signal to the other scanning lines.

Claim 5

A driving device according to claim 2, wherein said control means comprises a counter for counting the number of designations of the scanning lines.

Claim 6

A driving device, comprising: matrix electrodes composed of scanning lines and information lines; an information line driving circuit having a delay circuit for delaying the transfer of image information corresponding to writing into pixels of a scanning line, a serial-parallel converting circuit, and a first memory for storing the image information from the serial-parallel converting circuit; a scanning line driving circuit having a scanning line designating circuit for designating a scanning line, and a second memory for storing the designated scanning line information from said scanning line designating circuit; and a control circuit for controlling said information line driving circuit and said scanning line driving circuit so that the image information stored in said first memory which is used for Nth scanning, the scanning line information from said scanning line designating circuit which is used to designate a scanning line for (N+1)th scanning, and the scanning line information stored in said second memory which is used to designate a scanning line for Nth scanning are synchronously output, and said scanning line information used to designate the scanning line for (N+1)th scanning is output during outputting of the scanning line information for Nth scanning, and pixels on the scanning line designated by the scanning line information used to designate the scanning line for (N+1)th scanning are erased, and pixels on the scanning line designated by the scanning line information for designating Nth scanning stored in said second memory are written according to said image information stored in said first memory used for Nth scanning and further controlling said information line driving circuit and said scanning line driving circuit, in case the same scanning line is designated in succession, so as to prohibit the transfer of the image information to said delay circuit and, during the application of the writing voltage signals to the pixels of the scanning line designated according to the information from said second memory, to apply a non-selection signal to the other scanning lines.

Claim 7

A driving device, comprising: matrix electrodes composed of scanning lines and information lines; an information line driving circuit having a delay circuit for delaying the transfer of image information corresponding to writing into pixels of a scanning line, a serial-parallel converting circuit, and a first memory for storing the image information from the serial-parallel converting circuit; a scanning line driving circuit having a scanning line designating circuit for designating a scanning line, and a second memory for storing the designated scanning line information from said scanning line designating circuit; and a control circuit for controlling said information line driving circuit and said scanning line driving circuit so that the image information stored in said first memory which is used for Nth scanning, the scanning line information from said scanning line designating circuit which is used to designate a scanning line for (N+1)th scanning, and the scanning line information stored in said second memory which is used to designate a scanning line for Nth scanning are synchronously output, and said scanning line information used to designate the scanning line for (N+1)th scanning is output during outputting of the scanning line information for Nth scanning, and pixels on the scanning line designated by the scanning line information used to designate the scanning line for (N+1)th scanning are erased, and pixels on the scanning line designated by the scanning line information for designating Nth scanning stored in said second memory are written according to said image information stored in said first memory used for Nth scanning and further controlling said information line driving circuit and said scanning line driving circuit, in case the same scanning line is designated in succession, so as to prohibit the transfer of the image information to said delay circuit and, during the application of the writing voltage signals to the pixels of the scanning line designated according to the information from said second memory, to apply a non-selection signal to the other scanning lines.

Claim 8

A driving device according to claim 4, wherein said control means comprises means for comparing the content of the entered scanning line address information.

Claim 9

A driving device, comprising: a liquid crystal cell comprising matrix electrodes composed of scanning lines and information lines and utilizing ferroelectric liquid crystal; an information line driving circuit having a delay circuit for delaying the transfer of image information corresponding to the writing into pixels of a scanning line, a serial-parallel converting circuit, and a first memory for storing the image information from the serial-parallel converting circuit; a scanning line driving circuit having a scanning line designating circuit for designating a scanning line, and a second memory for storing the designated scanning line information from said scanning line designating circuit; and control means for controlling said information line driving circuit and said scanning line driving circuit so that the image information stored in said first memory which is used for Nth scanning, the scanning line information from said scanning line designating circuit which is used to designate a scanning line for (N+1)th scanning, and the scanning line information stored in said second memory which is used to designate a scanning line for Nth scanning are synchronously output, and said scanning line information used to designate the scanning line for (N+1)th scanning is output during outputting of the scanning line information for Nth scanning, and pixels on the scanning line designated by the scanning line information used to designate the scanning line for (N+1)th scanning are erased, and pixels on the scanning line designated by the scanning line information for designating Nth scanning stored in said second memory are written according to said image information stored in said first memory used for Nth scanning.

Claim 10

A driving device, comprising: a liquid crystal cell comprising matrix electrodes composed of scanning lines and information lines and utilizing ferroelectric liquid crystal; an information line driving circuit having a delay circuit for delaying the transfer of image information corresponding to the writing into pixels of a scanning line, a serial-parallel converting circuit, and a first memory for storing the image information from the serial-parallel converting circuit; a scanning line driving circuit having a scanning line designating circuit for designating a scanning line, and a second memory for storing the designated scanning line information from said scanning line designating circuit; and control means for controlling said information line driving circuit and said scanning line driving circuit so that the image information stored in said first memory which is used for Nth scanning, the scanning line information from said scanning line designating circuit which is used to designate a scanning line for (N+1)th scanning, and the scanning line information stored in said second memory which is used to designate a scanning line for Nth scanning are synchronously output, and said scanning line information used to designate the scanning line for (N+1)th scanning is output during outputting of the scanning line information for Nth scanning, and pixels on the scanning line designated by the scanning line information used to designate the scanning line for (N+1)th scanning are erased, and pixels on the scanning line designated by the scanning line information for designating Nth scanning stored in said second memory are written according to said image information stored in said first memory used for Nth scanning.

Claim 11

A driving device, comprising: a liquid crystal cell comprising matrix electrodes composed of scanning lines and information lines and utilizing ferroelectric liquid crystal; an information line driving circuit having a delay circuit for delaying the transfer of image information corresponding to the writing into pixels of a scanning line, a serial-parallel converting circuit, and a first memory for storing the image information from said serial-parallel converting circuit; a scanning line driving circuit having a scanning line designating circuit for designating a scanning line, and a second memory for storing the designated scanning line information from said scanning line designating circuit; and control means for controlling said information line driving circuit and said scanning line driving circuit so that the image information stored in said first memory which is used for Nth scanning, the scanning line information from said scanning line designating circuit which is used to designate a scanning line for (N+1)th scanning, and the scanning line information stored in said second memory which is used to designate a scanning line for Nth scanning are synchronously output, and the scanning line information used to designate the scanning line for (N+1)th scanning is output during outputting of the scanning line information for Nth scanning, and pixels on the scanning line designated by the scanning line information used to designate the scanning line for (N+1)th scanning are erased, and pixels on the scanning line designated by the scanning line information for designating Nth scanning stored in said second memory are written according to said image information stored in said first memory used for Nth scanning, and further controlling said information line driving circuit and said scanning line driving circuit, when the number of designations of scanning lines reaches a predetermined number, so as to prohibit the transfer of the image information to the delay circuit and, during the application of writing voltage signals to the pixels of the scanning line designated according to the information from said second memory, so as to apply a non-selection signal to the other scanning lines.

Claim 12

A driving device, comprising: a liquid crystal cell comprising matrix electrodes composed of scanning lines and information lines and utilizing ferroelectric liquid crystal; an information line driving circuit having a delay circuit for delaying the transfer of image information corresponding to the writing into pixels of a scanning line, a serial-parallel converting circuit, and a first memory for storing the image information from said serial-parallel converting circuit; a scanning line driving circuit having a scanning line designating circuit for designating a scanning line, and a second memory for storing the designated scanning line information from said scanning line designating circuit; and control means for controlling said information line driving circuit and said scanning line driving circuit so that the image information stored in said first memory which is used for Nth scanning, the scanning line information from said scanning line designating circuit which is used to designate a scanning line for (N+1)th scanning, and the scanning line information stored in said second memory which is used to designate a scanning line for Nth scanning are synchronously output, and the scanning line information used to designate the scanning line for (N+1)th scanning is output during outputting of the scanning line information for Nth scanning, and pixels on the scanning line designated by the scanning line information used to designate the scanning line for (N+1)th scanning are erased, and pixels on the scanning line designated by the scanning line information for designating Nth scanning stored in said second memory are written according to said image information stored in said first memory used for Nth scanning, and further controlling said information line driving circuit and said scanning line driving circuit, when the number of designations of scanning lines reaches a predetermined number, so as to prohibit the transfer of the image information to the delay circuit and, during the application of writing voltage signals to the pixels of the scanning line designated according to the information from said second memory, so as to apply a non-selection signal to the other scanning lines.

Claim 13

A driving device according to claim 7, wherein said control means comprises a counter for counting the number of designations of the scanning lines.

Claim 14

A driving device, comprising: a liquid crystal cell comprising matrix electrodes composed of scanning lines and information lines and utilizing ferroelectric liquid crystals; an information line driving circuit having a delay circuit for delaying the transfer of image information corresponding to the writing into pixels of a scanning line, a serial-parallel converting circuit, and a first memory for storing the image information from the serial-parallel converting circuit; a scanning line driving circuit having a scanning line designating circuit for designating a scanning line, and a second memory for storing the designated scanning line information from said scanning line designating circuit; and control means for controlling said information line driving circuit and said scanning line driving circuit so that the image information stored in said first memory which is used for Nth scanning, the scanning line information from said scanning line designating circuit which is used to designate a scanning line for (N+1)th scanning, and the scanning line information stored in said second memory which is used to designate a scanning line for Nth scanning are synchronously output, and said scanning line information used to designate the scanning line for (N+1)th scanning is output during outputting of the scanning line information for Nth scanning, and pixels on the scanning line designated by the scanning line information used to designate the scanning line for (N+1)th scanning are erased, and pixels on the scanning line designated by the scanning line information for designating Nth scanning stored in said second memory are written according to said image information stored in said first memory used for Nth scanning, and further controlling said information line driving circuit and said scanning line driving circuit, in case the same scanning line is designated in succession, so as to prohibit the transfer of the image information to the delay circuit and, during the application of writing voltage signals to the pixels of the scanning line designated according to the information from said second memory, to apply a non-selection signal to the other scanning lines.

Claim 15

A driving device, comprising: a liquid crystal cell comprising matrix electrodes composed of scanning lines and information lines and utilizing ferroelectric liquid crystals; an information line driving circuit having a delay circuit for delaying the transfer of image information corresponding to the writing into pixels of a scanning line, a serial-parallel converting circuit, and a first memory for storing the image information from the serial-parallel converting circuit; a scanning line driving circuit having a scanning line designating circuit for designating a scanning line, and a second memory for storing the designated scanning line information from said scanning line designating circuit; and control means for controlling said information line driving circuit and said scanning line driving circuit so that the image information stored in said first memory which is used for Nth scanning, the scanning line information from said scanning line designating circuit which is used to designate a scanning line for (N+1)th scanning, and the scanning line information stored in said second memory which is used to designate a scanning line for Nth scanning are synchronously output, and said scanning line information used to designate the scanning line for (N+1)th scanning is output during outputting of the scanning line information for Nth scanning, and pixels on the scanning line designated by the scanning line information used to designate the scanning line for (N+1)th scanning are erased, and pixels on the scanning line designated by the scanning line information for designating Nth scanning stored in said second memory are written according to said image information stored in said first memory used for Nth scanning, and further controlling said information line driving circuit and said scanning line driving circuit, in case the same scanning line is designated in succession, so as to prohibit the transfer of the image information to the delay circuit and, during the application of writing voltage signals to the pixels of the scanning line designated according to the information from said second memory, to apply a non-selection signal to the other scanning lines.

Claim 16

A driving device according to claim 9, wherein said control means comprises means for comparing the content of the entered scanning line address information.

Claim 17

A display system, comprising: a display panel comprising matrix electrodes composed of scanning lines and information lines; first means for transferring scanning line address information and image information corresponding to the writing into pixels of a scanning line; second means for delaying the transfer of the received image information and then latching the image information of a scanning line; and third means for decoding (N+1)th scanning address information received, outputting the encoded (N+1)th scanning address information as an encoded (N+1)th address signal to a scanning signal generation circuit, applying a (N+1)th first scanning selection signal by which an erase operation of pixels on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said (N+1)th address signal, storing said decoded (N+1)th first signal in a memory, outputting to the scanning signal generation circuit an encoded Nth address signal corresponding to Nth received scanning address information previously stored in said memory, and applying an Nth second scanning selection signal by which a writing operation on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said Nth address signal, with the Nth second scanning selection signal being formed by a voltage wave different from the first scanning selection signal.

Claim 18

A display system, comprising: a display panel comprising matrix electrodes composed of scanning lines and information lines; first means for transferring scanning line address information and image information corresponding to the writing into pixels of a scanning line; second means for delaying the transfer of the received image information and then latching the image information of a scanning line; and third means for decoding (N+1)th scanning address information received, outputting the encoded (N+1)th scanning address information as an encoded (N+1)th address signal to a scanning signal generation circuit, applying a (N+1)th first scanning selection signal by which an erase operation of pixels on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said (N+1)th address signal, storing said decoded (N+1)th first signal in a memory, outputting to the scanning signal generation circuit an encoded Nth address signal corresponding to Nth received scanning address information previously stored in said memory, and applying an Nth second scanning selection signal by which a writing operation on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said Nth address signal, with the Nth second scanning selection signal being formed by a voltage wave different from the first scanning selection signal.

Claim 19

A display system according to claim 11, wherein said display panel has a memory effect.

Claim 20

A display system according to claim 11, wherein said display panel comprises ferroelectric liquid crystal.

Claim 21

A display system according to claim 11, further comprising means for overlapping said (N+1)th first scanning selection signal and said Nth second scanning selection signal so as to be outputted.

Claim 22

A display system according to claim 14, wherein said display panel has a memory effect.

Claim 23

A display system according to claim 14, wherein said display panel comprises ferroelectric liquid crystal.

Claim 24

A display system, comprising: a display panel comprising matrix electrodes composed of scanning lines and information lines; first means for transferring scanning line address information and image information corresponding to the writing into pixels of a scanning line; second means for delaying the transfer of the received image information and then latching the image information of a scanning line; third means for decoding (N+1)th scanning address information received, outputting the encoded (N+1)th scanning address information as an encoded (N+1)th address signal to a scanning signal generation circuit, applying a (N+1)th first scanning selection signal by which an erase operation of pixels on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said (N+1)th address signal, storing said decoded (N+1)th first signal in a memory, outputting to the scanning signal generation circuit an encoded Nth address signal corresponding to Nth received scanning address information previously stored in said memory, and applying an Nth second scanning selection signal by which a writing operation on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said Nth address signal, with the Nth second scanning selection signal being formed by a voltage wave from different from the first scanning selection signal; and fourth means for disenabling an address signal designating selection of a scanning line to which the first selection signal is applied when a designation number of the scanning line designated in accordance with said scanning address information reaches a predetermined number.

Claim 25

A display system, comprising: a display panel comprising matrix electrodes composed of scanning lines and information lines; first means for transferring scanning line address information and image information corresponding to the writing into pixels of a scanning line; second means for delaying the transfer of the received image information and then latching the image information of a scanning line; third means for decoding (N+1)th scanning address information received, outputting the encoded (N+1)th scanning address information as an encoded (N+1)th address signal to a scanning signal generation circuit, applying a (N+1)th first scanning selection signal by which an erase operation of pixels on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said (N+1)th address signal, storing said decoded (N+1)th first signal in a memory, outputting to the scanning signal generation circuit an encoded Nth address signal corresponding to Nth received scanning address information previously stored in said memory, and applying an Nth second scanning selection signal by which a writing operation on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said Nth address signal, with the Nth second scanning selection signal being formed by a voltage wave from different from the first scanning selection signal; and fourth means for disenabling an address signal designating selection of a scanning line to which the first selection signal is applied when a designation number of the scanning line designated in accordance with said scanning address information reaches a predetermined number.

Claim 26

A display system according to claim 17, wherein said display panel has a memory effect.

Claim 27

A display system according to claim 17, wherein said display panel comprises ferroelectric liquid crystal.

Claim 28

A display system, comprising: a display panel comprising matrix electrodes composed of scanning lines and information lines; first means for transferring scanning line address information and image information corresponding to the writing into pixels of a scanning line; second means for delaying the transfer of the received image information and then latching the image information of a scanning line; third means for decoding (N+1)th scanning address information received, outputting the encoded (N+1)th scanning address information as an encoded (N+1)th address signal to a scanning signal generation circuit, applying a (N+1)th first scanning selection signal by which an erase operation of pixels on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said (N+1)th address signal, storing said decoded (N+1)th first signal in a memory, outputting to the scanning signal generation circuit an encoded Nth address signal corresponding to Nth received scanning address information previously stored in said memory, and applying an Nth second scanning selection signal by which a writing operation on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said Nth address signal, with the Nth second scanning selection signal being formed by a voltage wave from different from the first scanning selection signal; and fourth means for disenabling an address signal designating selection of a scanning line to which the first selection signal is applied when a designation number of the scanning line designated in accordance with said scanning address information reaches a predetermined number.

Claim 29

A display system, comprising: a display panel comprising matrix electrodes composed of scanning lines and information lines; first means for transferring scanning line address information and image information corresponding to the writing into pixels of a scanning line; second means for delaying the transfer of the received image information and then latching the image information of a scanning line; third means for decoding (N+1)th scanning address information received, outputting the encoded (N+1)th scanning address information as an encoded (N+1)th address signal to a scanning signal generation circuit, applying a (N+1)th first scanning selection signal by which an erase operation of pixels on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said (N+1)th address signal, storing said decoded (N+1)th first signal in a memory, outputting to the scanning signal generation circuit an encoded Nth address signal corresponding to Nth received scanning address information previously stored in said memory, and applying an Nth second scanning selection signal by which a writing operation on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said Nth address signal, with the Nth second scanning selection signal being formed by a voltage wave from different from the first scanning selection signal; and fourth means for disenabling an address signal designating selection of a scanning line to which the first selection signal is applied when a designation number of the scanning line designated in accordance with said scanning address information reaches a predetermined number.

Claim 30

A display system according to claim 20, wherein said display panel has a memory effect.

Claim 31

A display system according to claim 20, wherein said display panel comprises ferroelectric liquid crystal.

Claim 32

A display system, comprising: a display panel comprising matrix electrodes composed of scanning lines and information lines; first means for transferring scanning line address information and image information corresponding to the writing into pixels of a scanning line; second means for delaying the transfer of the received image information and then latching the image information of a scanning line; third means for decoding (N+1)th scanning address information received, outputting the encoded (N+1)th scanning address information as an encoded (N+1)th address signal to a scanning signal generation circuit, applying a (N+1)th first scanning selection signal by which an erase operation of pixels on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said (N+1)th address signal, storing said decoded (N+1)th first signal in a memory, outputting to the scanning signal generation circuit an encoded Nth address signal corresponding to Nth received scanning address information previously stored in said memory, and applying an Nth second scanning selection signal by which a writing operation on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said nth address signal, with the Nth second scanning selection signal being formed by a voltage wave from different from the first scanning selection signal; and fourth means for controlling said second and third means so as to stop output of said first scanning selection signal and output a non-selection signal when designation of the scanning line designated in accordance with said scanning address information is generated so as to continuously designated the same scanning line.

Claim 33

A display system, comprising: a display panel comprising matrix electrodes composed of scanning lines and information lines; first means for transferring scanning line address information and image information corresponding to the writing into pixels of a scanning line; second means for delaying the transfer of the received image information and then latching the image information of a scanning line; third means for decoding (N+1)th scanning address information received, outputting the encoded (N+1)th scanning address information as an encoded (N+1)th address signal to a scanning signal generation circuit, applying a (N+1)th first scanning selection signal by which an erase operation of pixels on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said (N+1)th address signal, storing said decoded (N+1)th first signal in a memory, outputting to the scanning signal generation circuit an encoded Nth address signal corresponding to Nth received scanning address information previously stored in said memory, and applying an Nth second scanning selection signal by which a writing operation on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said nth address signal, with the Nth second scanning selection signal being formed by a voltage wave from different from the first scanning selection signal; and fourth means for controlling said second and third means so as to stop output of said first scanning selection signal and output a non-selection signal when designation of the scanning line designated in accordance with said scanning address information is generated so as to continuously designated the same scanning line.

Claim 34

A display system according to claim 23, wherein said display panel has a memory effect.

Claim 35

A display system according to claim 23, wherein said display panel comprises ferroelectric liquid crystal.

Claim 36

A display system, comprising: a display panel comprising matrix electrodes composed of scanning lines and information lines; first means for transferring scanning line address information and image information corresponding to the writing into pixels of a scanning line; second means for delaying the transfer of the received image information and then latching the image information of a scanning line; third means for decoding (N+1)th scanning address information received, outputting the encoded (N+1)th scanning address information as an encoded (N+1)th address signal to a scanning signal generation circuit, applying a (N+1)th first scanning selection signal by which an erase operation of pixels on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said (N+1)th address signal, storing said decoded (N+1)th first signal in a memory, outputting to the scanning signal generation circuit an encoded Nth address signal corresponding to Nth received scanning address information previously stored in said memory, and applying an Nth second scanning selection signal by which a writing operation on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said Nth address signal, with the Nth second scanning selection signal being formed by a voltage wave from different from the first scanning selection signal; and fourth means for disenabling an address signal designating selection of a scanning line to which the first selection signal is applied when a designation number of the scanning line designated in accordance with said scanning address information reaches a predetermined number.

Claim 37

A display system, comprising: a display panel comprising matrix electrodes composed of scanning lines and information lines; first means for transferring scanning line address information and image information corresponding to the writing into pixels of a scanning line; second means for delaying the transfer of the received image information and then latching the image information of a scanning line; third means for decoding (N+1)th scanning address information received, outputting the encoded (N+1)th scanning address information as an encoded (N+1)th address signal to a scanning signal generation circuit, applying a (N+1)th first scanning selection signal by which an erase operation of pixels on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said (N+1)th address signal, storing said decoded (N+1)th first signal in a memory, outputting to the scanning signal generation circuit an encoded Nth address signal corresponding to Nth received scanning address information previously stored in said memory, and applying an Nth second scanning selection signal by which a writing operation on a scanning line is performed from the scanning signal generation circuit to the scanning line designated in response to said Nth address signal, with the Nth second scanning selection signal being formed by a voltage wave from different from the first scanning selection signal; and fourth means for disenabling an address signal designating selection of a scanning line to which the first selection signal is applied when a designation number of the scanning line designated in accordance with said scanning address information reaches a predetermined number.

Claim 38

A display system according to claim 26, wherein said display panel has a memory effect.

Claim 39

A display system according to claim 26, wherein said display panel comprises ferroelectric liquid crystal.