Non-volatile semiconductor memory device

Claim 2

A non-volatile semiconductor memory device, comprising: a bus line; a plurality of bit lines coupled to said bus line; a cell transistor, connected between each of said bit lines and a word line, for storing electrical information; an output circuit, coupled to said bus line, for outputting a signal corresponding to the electrical information stored in said cell transistor when said bus line has been charged to a predetermined voltage level; a constant voltage circuit coupled to said bus line, the constant voltage circuit generating a voltage having an approximately constant level when a current flows through said constant voltage circuit; and a current supply circuit, coupled to said bus line, for supplying a current to said constant voltage circuit via said bus line in accordance with a control signal supplied from an external unit, wherein said bus line is charged to a predetermined voltage level by the voltage generated by said constant voltage circuit, said current supply circuit being connected so as to receive the external control signal such that the external control signal controls said current supplied by said supply circuit and wherein said external control signal is a signal corresponding to an address transition detector signal.

Claim 3

A non-volatile semiconductor memory device as claimed in claim 1, wherein said current supply circuit comprises a voltage line maintained at a predetermined voltage level, and a switching circuit provided between said voltage line and said bus line, said switching circuit being turned on and off in accordance with the control signal, and wherein a current is supplied from said voltage line to said constant voltage circuit via said switching circuit and said bus line when said switching circuit is turned on.

Claim 4

A non-volatile semiconductor memory device as claimed in claim 1, wherein said constant voltage circuit comprises a plurality of elements connected in series between said bus line and a predetermined line so that a current flows from said bus line to said predetermined line through said plurality of elements, each of said plurality of elements generating a voltage having an approximately constant level, whereby a voltage having a constant level corresponding to a sum of voltages generated by said plurality of elements is applied across said bus line and said predetermined line.

Claim 5

A non-volatile semiconductor memory device as claimed in claim 3, wherein said plurality of elements includes a diode.

Claim 6

A non-volatile semiconductor memory device as claimed in claim 3, wherein said plurality of elements includes a transistor.

Claim 7

A non-volatile semiconductor memory device as claimed in claim 1, wherein said constant voltage circuit comprises two diodes connected in series between said bus line and a predetermined line so that a current flows from said bus line to said predetermined line through said two diodes.

Claim 8

A non-volatile semiconductor memory device as claimed in claim 1, wherein said constant voltage circuit comprises a diode and a transistor connected in series between said bus line and a predetermined line so that a current flows from said bus line to said predetermined line through said diode and said transistor.

Claim 9

A non-volatile semiconductor memory device as claimed in claim 7, wherein a voltage level generated by said diode is greater than a voltage level generated by said transistor.

Claim 10

A non-volatile semiconductor memory device, comprising: a bus line; a plurality of bit lines coupled to said bus line; a plurality of cell transistors, each connected between a corresponding one of said plurality of bit lines and a word line, for storing electrical information; an output circuit, coupled to said bus line, for outputting a signal corresponding to the electrical information stored in said plurality of cell transistors when said bus line has been charged to a predetermined voltage level; a constant voltage circuit coupled to said bus line, generating the predetermined voltage level for said bus line, the predetermined voltage level being substantially constant; control means for controlling storing and reading of the electrical information in said plurality of cell transistors; and a current supply circuit coupled to said bus line and to said control means, for supplying a current to said constant voltage circuit via said bus line, wherein said bus line is charged to the predetermined voltage level by said constant voltage circuit, said control means being connected to said current supply circuit so as to control said current supply circuit thereby controlling said constant voltage circuit and wherein said current supply circuit supplies the current to the constant voltage circuit in accordance with a signal corresponding to an address transition detector signal from said control means.

Claim 11

A non-volatile semiconductor memory device, comprising: a bus line; a plurality of bit lines coupled to said bus line; a plurality of cell transistors, each connected between a corresponding one of said plurality of bit lines and a word line, for storing electrical information; an output circuit, coupled to said bus line, for outputting a signal corresponding to the electrical information stored in said plurality of cell transistors when said bus line has been charged to a predetermined voltage level; a constant voltage circuit coupled to said bus line, generating the predetermined voltage level for said bus line, the predetermined voltage level being substantially constant; control means for controlling storing and reading of the electrical information in said plurality of cell transistors; and a current supply circuit coupled to said bus line and to said control means, for supplying a current to said constant voltage circuit via said bus line, wherein said bus line is charged to the predetermined voltage level by said constant voltage circuit, said control means being connected to said current supply circuit so as to control said current supply circuit thereby controlling said constant voltage circuit and wherein said current supply circuit supplies the current to the constant voltage circuit in accordance with a signal corresponding to an address transition detector signal from said control means.

Claim 12

A non-volatile semiconductor memory device as claimed in claim 9, wherein said current supply circuit comprises a voltage line maintained at a predetermined supply voltage level, and a switching circuit provided between said voltage line and said bus line, said switching circuit being turned on and off by said control means, and wherein a current is supplied from said voltage line to said constant voltage circuit via said switching circuit and said bus line when said switching circuit is turned on.

Claim 13

A non-volatile semiconductor memory device as claimed in claim 9, wherein said constant voltage circuit comprises a plurality of elements connected in series between said bus line and a predetermined line so that a current flows from said bus line to said predetermined line through said plurality of elements, each of said plurality of elements generating a voltage having an approximately constant level, whereby a voltage having a constant level corresponding to a sum of voltages generated by said plurality of elements is applied across said bus line and said predetermined line.

Claim 14

A non-volatile semiconductor memory device as claimed in claim 11, wherein said plurality of elements includes a diode.

Claim 15

A non-volatile semiconductor memory device as claimed in claim 11, wherein said plurality of elements includes a transistor.

Claim 16

A non-volatile semiconductor memory device as claimed in claim 9, wherein said constant voltage circuit comprises two diodes connected in series between said bus line and a predetermined line so that a current flows from said bus line to said predetermined line through said two diodes.

Claim 17

A non-volatile semiconductor memory device as claimed in claim 9, wherein said constant voltage circuit comprises a diode and a transistor connected in series between said bus line and a predetermined line so that a current flows from said bus line to said predetermined line through said diode and said transistor.

Claim 18

A non-volatile semiconductor memory device as claimed in claim 15, wherein a voltage level generated by said diode is greater than a voltage level generated by said transistor.