US5353429A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cache memory systems that accesses main memory without wait states during cache misses, using a state machine and address latch in the memory controller
Assignee: Apple Inc
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Filing: 1993-08-20
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Granted: 1994-10-04
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Expires: 2013-08-20
Abstract
Abstract A memory system where a cache miss is fielded with a retry access to main memory, but instead of waiting for the microprocessor to resynchronize and re-initiate the memory cycle, the memory cycle is started immediately. The speed of the tag array is specified so that the status of the cache, hit or miss, is known at the same time that the microprocessor's memory cycle start signal is known to be valid. The addresses are then latched and the memory cycle is started in anticipation of the retried cycle. The access time of memory is then overlapped with microprocessor resynchronization and memory cycle reinitialization. By using this technique, clock cycles are needed for the initial cycle, additional clock cycles are needed to perform the resynchronization, and additional clock cycles are needed for the retried cycle since the data is already waiting from memory. The above-described improvement is implemented by decoupling the direct connection of the memory array from the address bus. Additionally, a state machine modifies the operation of the memory controller so that the access time of the memory is overlapped with microprocessor resynchronization and memory cycle reinitialization.
Inventors
- 👤 Jonathan M. Fitch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:36
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0877; G06F12/0884
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
257 words
A computer system including a cache memory system comprising: a) a central processing unit coupled to a data bus and an address bus; b) a main memory having a predetermined access time coupled to said data bus and to an address latch bus, said main memory for storing data and instructions for use by said central processing unit; c) a memory controller means for controlling accesses to said main memory, said memory controller means including i) an address latch coupled to said address bus and said address latch bus, and ii) state machine means for controlling the operation of the memory controller means and the address latch; d) a cache memory means coupled to said address bus and said data bus for storing a predetermined subset of said data and instructions for use by said central processing unit; e) a cache tag array means coupled to said address bus for storing portions of addresses from said address bus corresponding to addresses of data and instructions stored in said cache memory means and for generating signals indicating for an address on said address bus whether data corresponding to the address on the address bus is stored within said cache memory means, such that if said data corresponding to the address on the address bus is not stored within said cache memory means, said state machine operates to cause the access time of said main memory to be overlapped with resynchronization of said central processing unit and memory cycle reinitialization required to obtain the data from said main memory.
Claim 2
Dependent Claim
257 words
A computer system including a cache memory system comprising: a) a central processing unit coupled to a data bus and an address bus; b) a main memory having a predetermined access time coupled to said data bus and to an address latch bus, said main memory for storing data and instructions for use by said central processing unit; c) a memory controller means for controlling accesses to said main memory, said memory controller means including i) an address latch coupled to said address bus and said address latch bus, and ii) state machine means for controlling the operation of the memory controller means and the address latch; d) a cache memory means coupled to said address bus and said data bus for storing a predetermined subset of said data and instructions for use by said central processing unit; e) a cache tag array means coupled to said address bus for storing portions of addresses from said address bus corresponding to addresses of data and instructions stored in said cache memory means and for generating signals indicating for an address on said address bus whether data corresponding to the address on the address bus is stored within said cache memory means, such that if said data corresponding to the address on the address bus is not stored within said cache memory means, said state machine operates to cause the access time of said main memory to be overlapped with resynchronization of said central processing unit and memory cycle reinitialization required to obtain the data from said main memory.
Claim 3
Dependent Claim
67 words
The computer system defined by claim 1 wherein said state machine means includes a first loop with an idle state, a cache miss state, a continue memory access state and a retry line fill state, and a second loop with said idle state and a cache hit state, and addresses within said address latch are placed onto said address latch bus only during said cache miss state.
Claim 4
Dependent Claim
37 words
The computer system defined by claim 2 wherein said state machine generates an address latch enable signal during said cache miss state which causes an address on said address bus to be latched by said address latch.
Claim 5
Dependent Claim
45 words
The computer system defined by claim 2 wherein during said retry line fill state, data on said data bus is written to said cache memory means and a predetermined portion of the address on said address bus is written to said cache tag array means.
Claim 6
Dependent Claim
241 words
In a computer system including a cache memory, a central processing unit coupled to a data bus and an address bus, a main memory having a predetermined access time coupled to said data bus and to an address latch bus, said main memory for storing data and instructions for use by said central processing unit, a memory controller for controlling accesses to said main memory, said memory controller including i) an address latch coupled to said address bus and said address latch bus, and ii) a state machine for controlling the operation of the memory controller and the address latch, a method for improving performance of said computer system during read operations comprising the steps of: a) storing a predetermined subset of said data and instructions for use by said central processing unit in said cache memory; b) storing portions of addresses from said address bus corresponding to addresses of data and instructions stored in said cache memory; c) generating signals indicating for an address on said address bus whether data corresponding to the address on the address bus is stored within said cache memory; d) wherein if said data corresponding to the address on the address bus is not stored within said cache memory, said state machine operating to cause the access time of said main memory to be overlapped with resynchronization of said central processing unit and memory cycle reinitialization required to obtain the data from said main memory.
Claim 7
Dependent Claim
241 words
In a computer system including a cache memory, a central processing unit coupled to a data bus and an address bus, a main memory having a predetermined access time coupled to said data bus and to an address latch bus, said main memory for storing data and instructions for use by said central processing unit, a memory controller for controlling accesses to said main memory, said memory controller including i) an address latch coupled to said address bus and said address latch bus, and ii) a state machine for controlling the operation of the memory controller and the address latch, a method for improving performance of said computer system during read operations comprising the steps of: a) storing a predetermined subset of said data and instructions for use by said central processing unit in said cache memory; b) storing portions of addresses from said address bus corresponding to addresses of data and instructions stored in said cache memory; c) generating signals indicating for an address on said address bus whether data corresponding to the address on the address bus is stored within said cache memory; d) wherein if said data corresponding to the address on the address bus is not stored within said cache memory, said state machine operating to cause the access time of said main memory to be overlapped with resynchronization of said central processing unit and memory cycle reinitialization required to obtain the data from said main memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-03 | 1998-04-04 | 1998-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-03 | 2002-04-04 | 2002-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-03 | 2006-04-04 | 2006-10-04 | $7700.00 | Window Closed / Lapsed |