Electrically erasable programmable read-only memory with an array of one-transistor memory cells

Claim 2

An electrically erasable and programmable transistor comprising: a semiconductive substrate; a source and a drain spaced apart to define a channel region therebetween in said substrate; an insulated conductive layer at least partially overlying the channel region and being capacitively coupled with said substrate; a control gate insulatively disposed above the conductive layer and spanning the channel region; and said drain being doped with an impurity at a specifically selected density which causes the withstanding voltage of said drain to be potentially greater than a first voltage applied to said drain during a read operation and to be less than a second voltage applied thereto for forcing said conductive layer to discharge.

Claim 3

A transistor according to claim 1, wherein said drain is doped with an impurity at a specific density which causes said withstanding voltage to be potentially greater than the first voltage and less than the second voltage.

Claim 4

A transistor according to claim 2, wherein said source and said drain are opposite in conductivity type to said substrate.

Claim 5

A transistor according to claim 3, wherein said source and said drain are spaced apart at a certain distance which is on the order of submicrons.

Claim 6

A transistor according to claim 4, further comprising: a dielectric layer between said substrate and said conductive layer, said dielectric layer being thin enough to allow charge particles to tunnel to or from said conductive layer.

Claim 7

A transistor according to claim 5, wherein said source and said drain are substantially self-aligned cross-sectionally with said conductive layer and said control gate.

Claim 8

An electrically erasable and programmable memory device comprising: a semiconductive substrate; an array of memory cells arranged in rows and columns on said substrate, said array being divided into a plurality of blocks each of which includes a preselected number of subarrays of series-connected memory cells with drain-side nodes and source-side nodes respectively; data transfer lines associated with the columns of memory cells; control lines associated with the row of memory cells; addressing means for designating a memory address by selecting one from among said data transfer lines and one from among said control lines respectively; and each of said memory cells essentially consisting of a metal oxide semiconductor transistor having, a source and a drain spaced apart in said substrate, an insulated floating carrier-storage layer above said substrate, a control gate insulatively disposed above said carrier-storage layer and, and said drain being doped with an impurity at a specifically selected density which causes the withstanding voltage of said drain to be potentially greater than a first voltage applied to said drain during a read operation and to be less than a second voltage applied thereto for forcing said carrier-storage layer to discharge.

Claim 9

An electrically erasable and programmable memory device comprising: a semiconductive substrate; an array of memory cells arranged in rows and columns on said substrate, said array being divided into a plurality of blocks each of which includes a preselected number of subarrays of series-connected memory cells with drain-side nodes and source-side nodes respectively; data transfer lines associated with the columns of memory cells; control lines associated with the row of memory cells; addressing means for designating a memory address by selecting one from among said data transfer lines and one from among said control lines respectively; and each of said memory cells essentially consisting of a metal oxide semiconductor transistor having, a source and a drain spaced apart in said substrate, an insulated floating carrier-storage layer above said substrate, a control gate insulatively disposed above said carrier-storage layer and, and said drain being doped with an impurity at a specifically selected density which causes the withstanding voltage of said drain to be potentially greater than a first voltage applied to said drain during a read operation and to be less than a second voltage applied thereto for forcing said carrier-storage layer to discharge.

Claim 10

A device according to claim 7, further comprising: first select means arranged between the drain-side nodes of said subarrays of series-connected memory cells and said data transfer lines, for selectively turning on to cause said subarrays to be connected with said data transfer lines.

Claim 11

A device according to claim 6, further comprising: second select means coupled between the source-side nodes of said subarrays and a common source voltage, for selectively turning on to cause said subarrays to be connected with the common source voltage.

Claim 12

A device according to claim 9, wherein each of said subarrays comprises a series circuit of memory cell transistors, thereby constituting a NAND cell unit.

Claim 13

A device according to claim 10, wherein each of said memory cell transistors comprises a floating-gate tunneling semiconductor field effect transistor.

Claim 14

A device according to claim 9, wherein each of said subarrays comprises memory cell transistors which are arranged such that a plurality of cells are connected in parallel with one another between a corresponding one of said data transfer lines and a source line, thereby constituting a NOR cell unit.

Claim 15

A device according to claim 10, further comprising: erase means connected to said data transfer lines and said control lines, for erasing a selected block among said blocks by causing punch-through phenomenon to take place in the memory cell transistors in the selected block, while the remaining ones of said blocks are prevented from being erased.

Claim 16

A device according to claim 13, wherein said erase means generates a first DC potential and a second DC potential which is higher than the first potential, the second potential being applied to the drain-side nodes of the NAND cell units via said data transfer lines associated therewith.

Claim 17

A device according to claim 14, wherein said erase means applies said first potential to said control lines.

Claim 18

A device according to claim 15, wherein said erase means includes a row decoder circuit which selectively produces said second potential.

Claim 19

A device according to claim 12, further comprising: a transistor for selecting said source line.

Claim 20

A device according to claim 12, further comprising: erase means for erasing a selected memory cell transistor by applying an "H" or High level voltage to one of said data transfer lines associated with the selected memory cell transistor, while causing an "L" or Low level voltage to be applied to said substrate, said source line, and a control gate of said selected memory cell transistor.

Claim 21

A device according to claim 10, further comprising: erase means for erasing a selected memory cell transistor by applying an "H" or High level voltage to a data transfer line associated with the selected memory cell transistor and to said first select means associated with said selected memory cell transistor, while causing an "L" or Low level voltage to be applied to (i) said second select means, (ii) a control gate of said selected memory cell transistor, and (iii) said first select means associated with a non-selected memory cell transistor.