Semiconductor memory device having redundant memory cells

Claim 1

A semiconductor memory device comprising: an array of memory cells; at least one redundant memory cell; a write access port, said write access port including addressing circuitry having an address input terminal for receiving a memory cell address, having a write decoder which generates a signal for accessing one of said memory cells of said array of memory cells in response to said memory cell address and said write decoder having the address of a defective memory cell stored therein in a nonvolatile manner, said write decoder generating a redundant write signal for accessing said redundant memory cell rather than said defective memory cell when said memory cell address corresponds to said address of said defective memory cell; a register responsive to said redundant write signal, said register storing said memory cell address when said memory cell address corresponds to said address of said defective memory cell in response to said redundant write signal; a plurality of read access ports each read access port including addressing circuitry for each of said read access ports, said addressing circuitry for each of said read access ports including a read decoder for selecting one memory cell of said array of memory cells to be addressed in response to an address signal provided on an address port, and a comparator, said comparator having a first input connected to said address port and a second input connected to said register, said comparator providing a redundant access signal to said read decoder which causes access to be provided to said redundant memory cell when said address signal and the address stored in said register correspond.