US5359694A
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Method and apparatus for converting image data
Assignee: Atmel Corp
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Filing: 1992-07-27
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Granted: 1994-10-25
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Expires: 2012-07-27
Abstract
Abstract A method and apparatus for converting input image data in line-scan format into block-scan format, and for converting input image data in block-scan format into line-scan format. The apparatus can be implemented as a single integrated circuit which includes a memory and control logic for implementing format conversion, but no external address lines. The apparatus includes an address generator which automatically generates an address sequence for each strip of input data. Each input data strip comprises N lines of image data words, with L vectors in each line, where each vector comprises M image data words. The apparatus converts a line-scan format input data strip into blocks each consisting of N vectors. Each input data strip is processed efficiently, by automatically generating a sequence of addresses for the vectors of the strip. During each iteration of a format conversion operation, one address is generated, one vector is read out of a memory location identified by that address, and one input vector is written into the memory location. The address generator preferably generates addresses for B input data strips which comprise an image by performing a sequence of iterations during each of B cycles, where each iteration includes the step of "modulo k" addition by an increment F, where F has a different value during each cycle. The increment F for each of the cycles following the first cycle is stored as it becomes available during performance of a previous one of the cycles.
Inventors
- 👤 Gilles Concordel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:11
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/04; H04N1/0402; H04N1/0417; H04N19/00; H04N19/42; H04N19/423; H04N19/60; H04N19/61; H04N19/85
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
345 words
An apparatus for converting strips of input image data in a first one of a line-scan format and a block-scan format, into output data having a second one of the line-scan format and the block-scan format, wherein B of the strips determine an input image, wherein each of the strips comprises N lines of image data words, and wherein each of the lines of image data words comprises L vectors, where B, N, and L are integers, said apparatus including:. a random access memory, having memory locations for a strip comprising a set of vectors of the input image data, each of said vectors comprising M words of the input image data, where M is an integer; and an address generator, wherein the random access memory and the address generator are implemented in a single integrated circuit, and wherein the address generator includes a means for generating a sequence of address signals for the vectors of a strip of the input image data during each cycle of a cyclical address generation operation, wherein said each cycle comprises a sequence of iterations, and wherein the address generator generates an address signal for a vector of the strip during each of the iterations, wherein the address generator includes means for generating a different sequence of address signals for each of at least two strips of the input image data, during different cycles of the cyclical address generation operation, and wherein the address generator includes a means for performing B cycles of the cyclical address generation operation to generate B sequences of address signals, with each of said iterations consisting of modulo k addition by an increment F, where k=NL-1, wherein the increment F has a different value during each of said B cycles, wherein the increment F for a first one of the B cycles is a default value, and the increment F for the Yth one of the B cycles, where Y is an integer greater than one is stored as said increment F is generated during performance of the (Y-1)th one of the B cycles.
Claim 2
Independent Claim
345 words
An apparatus for converting strips of input image data in a first one of a line-scan format and a block-scan format, into output data having a second one of the line-scan format and the block-scan format, wherein B of the strips determine an input image, wherein each of the strips comprises N lines of image data words, and wherein each of the lines of image data words comprises L vectors, where B, N, and L are integers, said apparatus including:. a random access memory, having memory locations for a strip comprising a set of vectors of the input image data, each of said vectors comprising M words of the input image data, where M is an integer; and an address generator, wherein the random access memory and the address generator are implemented in a single integrated circuit, and wherein the address generator includes a means for generating a sequence of address signals for the vectors of a strip of the input image data during each cycle of a cyclical address generation operation, wherein said each cycle comprises a sequence of iterations, and wherein the address generator generates an address signal for a vector of the strip during each of the iterations, wherein the address generator includes means for generating a different sequence of address signals for each of at least two strips of the input image data, during different cycles of the cyclical address generation operation, and wherein the address generator includes a means for performing B cycles of the cyclical address generation operation to generate B sequences of address signals, with each of said iterations consisting of modulo k addition by an increment F, where k=NL-1, wherein the increment F has a different value during each of said B cycles, wherein the increment F for a first one of the B cycles is a default value, and the increment F for the Yth one of the B cycles, where Y is an integer greater than one is stored as said increment F is generated during performance of the (Y-1)th one of the B cycles.
Claim 3
Dependent Claim
77 words
The apparatus of claim 1, wherein the address generator is operable in a mode for converting strips of the input image data in line-scan format to output data having block-scan format, and wherein in said mode, for the Yth one of the B cycles, where Y is an integer greater than one, the increment F has value equal to said default value multiplied by the result of modulo k multiplication of Y-1 factors of said integer L.
Claim 4
Dependent Claim
32 words
The apparatus of claim 2, wherein the address generator is also operable in a second mode for converting strips of input image data in block-scan format to output data having line-scan format.
Claim 5
Dependent Claim
13 words
The apparatus of claim 2, wherein the default value is equal to one.
Claim 6
Dependent Claim
77 words
The apparatus of claim 1, wherein the address generator is operable in a mode for converting strips of the input image data in block-scan format to output data having line-scan format, and wherein in said mode, for the Yth one of the B cycles, where Y is an integer greater than one, the increment F has value equal to said default value multiplied by the result of modulo k multiplication of Y-1 factors of said integer N.
Claim 7
Dependent Claim
13 words
The apparatus of claim 5, wherein the default value is equal to one.
Claim 8
Dependent Claim
7 words
The apparatus of claim 1, wherein M=N=8.
Claim 9
Dependent Claim
60 words
The apparatus of claim 1, wherein the address generator asserts said address signal to the random access memory during said iteration to cause a read of data from a memory location of the random access memory identified by said address signal during said iteration, and to cause an incoming vector to be written into said memory location during said iteration.
Claim 10
Dependent Claim
26 words
The apparatus of claim 8, wherein the address generator asserts said address signal to the random access memory conditionally to an externally provided package identification signal.
Claim 11
Dependent Claim
159 words
The apparatus of claim 9, also including: a second random access memory, having memory locations for a strip comprising a set of vectors of the input image data, each of said vectors comprising M words of the input image data; and a second address generator, wherein the second random access memory and the second address generator are implemented in a second single integrated circuit cascaded with said single integrated circuit, and wherein the second address generator includes means for generating a sequence of address signals for the vectors of a strip of the input image data during each cycle of a cyclical address generation operation, wherein said each cycle comprises a sequence of iterations, wherein the second address generator generates an address signal for a vector of the strip during each of the iterations, and wherein the second address generator asserts said address signal to the second random access memory conditionally to a second externally provided package identification signal.
Claim 12
Dependent Claim
74 words
(Amended) The apparatus of claim 1, also including: pixel format conversion means for receiving pixel-interleaved color raster scan format image data, deinterleaving words of each line of the pixel-interleaved color raster scan data and transferring vectors of input image data to the random access memory; and vector format conversion means for receiving the output data from the random access memory and deinterleaving vectors of said output data to generate minimum coded unit-scan format data.
Claim 13
Dependent Claim
69 words
The apparatus of claim 1, also including: vector format conversion means for receiving minimum coded unit-scan format data, interleaving vectors of the minimum coded unit-scan format data and transferring vector-interleaved blocks of input image data to the random access memory; and pixel format conversion means for receiving the output data from the random access memory and interleaving said output data to generate pixel-interleaved color raster scan format image data.
Claim 14
Independent Claim
236 words
An apparatus for converting strips of input image data in a first one of a line-scan format and a block-scan format, into output data having a second one of the line-scan format and the block-scan format, said apparatus including: a random access memory, having memory locations for a strip comprising vectors of the input image data, each of said vectors comprising M words of the input image data, where M is an integer; and an address generator connected to the random access memory, and including means for performing B cycles of an address generation operation to generate B sequences of address signals for vectors of each of B strips of the input image data, where B is an integer greater than one, wherein each of the cycles includes a sequence of iterations, and wherein the address generator generates one of said address signals for one of the vectors during each of the iterations, wherein each of said strips comprises N lines of image data words, each of said lines of image data words comprises L vectors, where N and L are integers, and wherein each of the iterations includes an operation of modulo k addition by an increment F, where k=NL-1 wherein the increment F for one of the B cycles, where Y is an integer greater than one, is stored as said increment F is generated during performance of the one of the B Cycles.
Claim 15
Independent Claim
236 words
An apparatus for converting strips of input image data in a first one of a line-scan format and a block-scan format, into output data having a second one of the line-scan format and the block-scan format, said apparatus including: a random access memory, having memory locations for a strip comprising vectors of the input image data, each of said vectors comprising M words of the input image data, where M is an integer; and an address generator connected to the random access memory, and including means for performing B cycles of an address generation operation to generate B sequences of address signals for vectors of each of B strips of the input image data, where B is an integer greater than one, wherein each of the cycles includes a sequence of iterations, and wherein the address generator generates one of said address signals for one of the vectors during each of the iterations, wherein each of said strips comprises N lines of image data words, each of said lines of image data words comprises L vectors, where N and L are integers, and wherein each of the iterations includes an operation of modulo k addition by an increment F, where k=NL-1 wherein the increment F for one of the B cycles, where Y is an integer greater than one, is stored as said increment F is generated during performance of the one of the B Cycles.
Claim 16
Dependent Claim
36 words
The apparatus of claim 13, wherein the increment F has a different value during each of said B cycles, and wherein the increment F for a first one of the B cycles is a default value.
Claim 17
Dependent Claim
77 words
The apparatus of claim 13, wherein the address generator is operable in a mode for converting strips of the input image data in line-scan format to output data having block-scan format, and wherein in said mode, for the Yth one of the B cycles, where Y is an integer greater than one, the increment F has value equal to said default value multiplied by the result of modulo k multiplication of Y-1 factors of said integer L.
Claim 18
Dependent Claim
77 words
The apparatus of claim 13, wherein the address generator is operable in a mode for converting strips of the input image data in block-scan format to output data having line-scan format, and wherein in said mode, for the Yth one of the B cycles, where Y is an integer greater than one, the increment F has value equal to said default value multiplied by the result of modulo k multiplication of Y-1 factors of said integer N.
Claim 19
Dependent Claim
13 words
The apparatus of claim 16, wherein the default value is equal to one.
Claim 20
Dependent Claim
7 words
The apparatus of claim 13, wherein M=N=8.
Claim 21
Dependent Claim
60 words
The apparatus of claim 16, wherein the address generator asserts said address signal to the random access memory during said iteration to cause a read of data from a memory location of the random access memory identified by said address signal during said iteration, and to cause an incoming vector to be written into said memory location during said iteration.
Claim 22
Dependent Claim
26 words
The apparatus of claim 19, wherein the address generator asserts said address signal to the random access memory conditionally to an externally provided package identification signal.
Claim 23
Independent Claim
210 words
A method for converting strips of input image data in a first one of a line-scan format and a block-scan format into output data having a second one of the line-scan format and the block-scan format, including the steps of: sequentially asserting B strips of the input image data to a memory, wherein each of the strips comprises N lines of vectors, each of said lines comprising L vectors, and each of said vectors comprising M words, wherein B, M, N, and L are integers, and wherein the memory has memory locations for storing each of the vectors of one of the strips; and performing B cycles of a cyclical address generation operation to generate sequences of address signals for the vectors of the B strips, wherein each of the cycles includes a sequence of iterations, wherein an address signal for a different one of the vectors is generated during each of the iterations, where each of the iterations includes an operation of modulo k addition by an increment F, where k=NL-1, wherein the increment F for the Yth one Of the B cycles, where Y is an integer greater than one is stored as said increment F is generated during performance of the (Y-1)th one of the B cycles.
Claim 24
Independent Claim
210 words
A method for converting strips of input image data in a first one of a line-scan format and a block-scan format into output data having a second one of the line-scan format and the block-scan format, including the steps of: sequentially asserting B strips of the input image data to a memory, wherein each of the strips comprises N lines of vectors, each of said lines comprising L vectors, and each of said vectors comprising M words, wherein B, M, N, and L are integers, and wherein the memory has memory locations for storing each of the vectors of one of the strips; and performing B cycles of a cyclical address generation operation to generate sequences of address signals for the vectors of the B strips, wherein each of the cycles includes a sequence of iterations, wherein an address signal for a different one of the vectors is generated during each of the iterations, where each of the iterations includes an operation of modulo k addition by an increment F, where k=NL-1, wherein the increment F for the Yth one Of the B cycles, where Y is an integer greater than one is stored as said increment F is generated during performance of the (Y-1)th one of the B cycles.
Claim 25
Dependent Claim
19 words
The method of claim 21, wherein the increment F has a different value during each of the B cycles.
Claim 26
Dependent Claim
21 words
The method of claim 21, wherein the increment F for a first one of the B cycles is a default value.
Claim 27
Dependent Claim
70 words
The method of claim 23, wherein during conversion of strips of the input image data in line-scan format to output data having block-scan format, for the Yth one of the B cycles, where Y is an integer greater than one, the increment F has a value equal to said default value of the increment F multiplied by the result of modulo k multiplication of Y-1 factors of said integer L.
Claim 28
Dependent Claim
70 words
The method of claim 23, wherein during conversion of strips of the input image data in block-scan format to output data having line-scan format, for the Yth one of the B cycles, where Y is an integer greater than one, the increment F has a value equal to said default value of the increment F multiplied by the result of modulo k multiplication of Y-1 factors of said integer N.
Claim 29
Dependent Claim
7 words
The method of claim 21, wherein M=N=8.
Claim 30
Dependent Claim
77 words
The method of claim 21, also including the steps of: asserting the address signal for said one of the vectors to the random access memory during said each of the iterations, thereby causing data to be read from a memory location of the random access memory identified by said address signal during said each of the iterations, and causing said one of the vectors to be written into said memory location during said each of the iterations.
Claim 31
Dependent Claim
30 words
The method of claim 27, wherein the address signal for said one of the vectors is asserted to the random access memory conditionally to an externally provided package identification signal.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-10-24 | 1998-04-25 | 1998-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-24 | 2002-04-25 | 2002-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-24 | 2006-04-25 | 2006-10-25 | $7700.00 | Window Closed / Lapsed |