US5361229A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Precharging bitlines for robust reading of latch data
Assignee: Xilinx Inc
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Filing: 1993-04-08
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Granted: 1994-11-01
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Expires: 2013-04-08
Abstract
Abstract The bit line for reading data in or writing data out from a CMOS integrated circuit latch is precharged to the trip point voltage of the latch (as determined by the latch's transistor design) shortly before the occurrence of a read operation. The precharging circuitry uses the latch circuit itself to generate the trip point, hence ensuring that the precharging circuit operates properly with regards to the latch characteristics in spite of temperature, voltage and fabrication process variations. The precharging circuitry ensures that during the operation of reading data from the latch, the bit line voltage never causes the latch to completely switch states, since at most the bit line voltage asymptotically approaches the trip point voltage. The precharging circuit is relatively simple, including only two logic gates and three other transistors.
Inventors
- 👤 David Chiang
- 👤 Wei-Yi Ku
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:14
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/12
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
53 words
A data storage circuit comprising: a latch; a write circuit for writing data into said latch on a conductor connected to said latch; a read circuit for reading the data from said conductor; and a precharge circuit connected to said conductor for charging said conductor to a trip point voltage of said latch.
Claim 2
Dependent Claim
53 words
A data storage circuit comprising: a latch; a write circuit for writing data into said latch on a conductor connected to said latch; a read circuit for reading the data from said conductor; and a precharge circuit connected to said conductor for charging said conductor to a trip point voltage of said latch.
Claim 3
Dependent Claim
41 words
The circuit of claim 1, wherein said precharge circuit includes a logic gate operatively connected to said read circuits and said write circuit, thereby allowing the charging of said conductor only when no writing or reading of the data is occurring.
Claim 4
Dependent Claim
38 words
The circuit of claim 1, wherein said precharge circuit includes a buffer having two field effect transistors each having an active area differing from and having a predetermined relation to the active area of transistors in said latch.
Claim 5
Dependent Claim
25 words
The circuit of claim 3, further comprising a switch for connecting an input terminal of said buffer to an output terminal thereof during the charging.
Claim 6
Independent Claim
74 words
A method of operating a latch for storing data written into said latch on a line connecting to said latch and which is to be read out of the latch on the line, comprising: generating a voltage at a trip point of said latch; determining a time when no reading or writing of the data is taking place; and at the determined time, connecting the generated voltage to said line, thereby charging said line.
Claim 7
Independent Claim
74 words
A method of operating a latch for storing data written into said latch on a line connecting to said latch and which is to be read out of the latch on the line, comprising: generating a voltage at a trip point of said latch; determining a time when no reading or writing of the data is taking place; and at the determined time, connecting the generated voltage to said line, thereby charging said line.
Claim 8
Dependent Claim
34 words
The method of claim 5, wherein said precharge circuit includes a buffer, and further comprising the step of: at the determined time, connecting an output terminal of said buffer to an input terminal thereof.
Claim 9
Dependent Claim
112 words
The circuit of claim 1, wherein said precharge circuit includes: a buffer having an input terminal and an output terminal; a first transistor connected between said input and output terminals of said buffer and having a gate terminal; a second transistor connected between a voltage source and said input terminal of said buffer and having a gate terminal; a third transistor connected between said output terminal of the buffer and said conductor and having a gate terminal; and a logic gate having two input terminals connected respectively to said read circuit and said write circuit, and having an output terminal connected to the gate terminals of said first, second, and third transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-31 | 1998-05-02 | 1998-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-31 | 2002-05-02 | 2002-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-31 | 2006-05-02 | 2006-11-01 | $7700.00 | Window Closed / Lapsed |