US5367639A
Expired / Lapsed
US
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Method and apparatus for dynamic chaining of DMA operations without incurring race conditions
Assignee: Sun Microsystems Inc
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Filing: 1991-12-30
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Granted: 1994-11-22
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Expires: 2011-12-30
Abstract
Abstract An apparatus and method for performing direct memory access (DMA) to input/output (I/O) devices are described. In order to overcome storage limitations of a DMA controller, channel control blocks (CCBs) are stored in external memory. The DMA controller is programmed to reference a particular address of the external memory when a predetermined bit, referred to as a chain bit, in a current channel control block is set. The DMA controller will then perform a memory read operation on that area of memory and store a retrieved channel control block at a location previously utilized by an earlier channel control block. This process will continue until the chain bit is reset, at which time a DMA operation is complete. Dynamic chaining is easily accommodated whereby channel control blocks can be dynamically changed during the DMA access to provide a flexible I/O system. The apparatus and method may be used to implement dynamic chaining without incurring race conditions. A wait bit is provided in each channel control block and, when this bit is set, the DMA controller will suspend operations thereby providing an opportunity for updating a chain of CCBs without incurring errors due to race conditions. Once the chain has been modified, the wait bit is reset and processing safely continues.
Inventors
- 👤 Martin Sodos
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:10
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/10; G06F13/12
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
298 words
In a computer system comprising a central processing unit (CPU), memory, and input/output (I/O) storage devices, an apparatus for performing direct memory access (DMA) to the I/O devices comprising: an I/O controller for performing DMA operations, said I/O controller comprising controller logic and a first channel control block (CCB) register, said first CCB register storing a channel control block (CCB) identifying DMA transfer parameters which specify an operation to be performed by the I/O controller, said controller logic performing operations in accordance with the CCB, said CCB comprising a chain status bit, which, when set, indicates to the controller logic that a subsequent operation is to be performed as specified by another channel control block, said first CCB register initially storing a first CCB; an I/O storage device external to the I/O controller comprising and storing at least one subsequent CCB to be processed subsequent to the first CCB; and a chip control status block coupled to the controller logic, said chip control status block comprising an external memory address pointer which specifies an address, in the I/O storage device external to the I/O controller, of a next CCB to be processed, said external memory address pointer being incremented after each access to a CCB in the I/O storage device external to the I/O controller to point to a next CCB to be processed; said I/O controller reading a CCB from the I/O storage device external to the I/O controller at the address specified by the external memory address pointer, storing that CCB in said first CCB register and performing operations in accordance with the CCB stored in the first CCB register; whereby the I/O controller performs a chain of operations specified by a chain of CCBs without increasing an amount of memory required in the I/O controller.
Claim 2
Dependent Claim
298 words
In a computer system comprising a central processing unit (CPU), memory, and input/output (I/O) storage devices, an apparatus for performing direct memory access (DMA) to the I/O devices comprising: an I/O controller for performing DMA operations, said I/O controller comprising controller logic and a first channel control block (CCB) register, said first CCB register storing a channel control block (CCB) identifying DMA transfer parameters which specify an operation to be performed by the I/O controller, said controller logic performing operations in accordance with the CCB, said CCB comprising a chain status bit, which, when set, indicates to the controller logic that a subsequent operation is to be performed as specified by another channel control block, said first CCB register initially storing a first CCB; an I/O storage device external to the I/O controller comprising and storing at least one subsequent CCB to be processed subsequent to the first CCB; and a chip control status block coupled to the controller logic, said chip control status block comprising an external memory address pointer which specifies an address, in the I/O storage device external to the I/O controller, of a next CCB to be processed, said external memory address pointer being incremented after each access to a CCB in the I/O storage device external to the I/O controller to point to a next CCB to be processed; said I/O controller reading a CCB from the I/O storage device external to the I/O controller at the address specified by the external memory address pointer, storing that CCB in said first CCB register and performing operations in accordance with the CCB stored in the first CCB register; whereby the I/O controller performs a chain of operations specified by a chain of CCBs without increasing an amount of memory required in the I/O controller.
Claim 3
Dependent Claim
139 words
The apparatus as set forth in claim 1, wherein, said I/O controller further comprises a second CCB register and said chip control status block further comprises a CCB register status bit to identify one of said first and second CCB registers as a CCB register currently being accessed; and said I/O controller, upon detection that the chain status bit in the CCB stored in the CCB register currently being accessed, retrieves the next CCB from the I/O storage device external to the I/O controller and stores that CCB in the other of the first and second CCB registers identified by the CCB register status bit as the CCB register not currently being accessed, and updates the CCB register status bit such that the other CCB register will subsequently be accessed; whereby double buffering of the CCB registers is performed.
Claim 4
Dependent Claim
106 words
The apparatus as set forth in claim 1 wherein said external memory address pointer specifies the address of a first subsequent CCB stored in the I/O storage device external to the I/O controller, said apparatus further comprising a CCB counter register which maintains a count of the number of CCBs processed, said CCB counter register incremented as each CCB is processed, the address of the next CCB in the I/O storage device external to the I/O controller determined from the address of the first subsequent CCB and the CCB counter register whereby the address of the next CCB is incremented by incrementing the CCB counter register.
Claim 5
Dependent Claim
27 words
The apparatus as set forth in claim 1, wherein after the last CCB is processed, the I/O controller restores the first CCB in the first CCB register.
Claim 6
Dependent Claim
55 words
The apparatus as set forth in claim 4, wherein the first CCB is stored at a predetermined location in the I/O storage device and the first CCB is read from the predetermined location in the I/O storage device and written into the first CCB register to restore the first CCB in the first CCB register.
Claim 7
Dependent Claim
45 words
The apparatus as set forth in claim 4 further comprising an initialize status bit, said initialize status bit checked at the beginning of a DMA operation wherein, if the initialize status bit is not set, the first CCB is restored in the first CCB register.
Claim 8
Dependent Claim
250 words
In a computer system comprising a central processing unit (CPU), memory, input/output I/O storage devices, and an I/O controller for performing direct memory access (DMA) operations with respect to the I/O storage devices, a method for performing direct memory access (DMA) to the I/O storage devices comprising: providing a first channel control block (CCB) register in the I/O controller, said first CCB register storing a first CCB identifying DMA transfer parameters which specify an operation to be performed by the I/O controller; providing a chain status bit in the CCB, which when set, indicates to the I/O controller that another CCB is to be subsequently processed; providing an external memory address pointer which specifies an address, in an I/O storage device external to the I/O controller, of a subsequent CCB to be processed; performing operations specified by the CCB stored in the first CCB register; reading the chain status bit; if the chain status bit is set, upon completion of performing operations, retrieving a next CCB from the I/O storage device external to the I/O controller at the address specified by the external memory pointer; storing the next CCB in the first CCB register; incrementing the address in the external memory address pointer to point to a next CCB in the I/O storage device external to the I/O controller to be processed; and processing the next CCB stored in the first CCB register; whereby chaining of CCBs is achieved without increasing an amount of memory required in the I/O controller.
Claim 9
Dependent Claim
250 words
In a computer system comprising a central processing unit (CPU), memory, input/output I/O storage devices, and an I/O controller for performing direct memory access (DMA) operations with respect to the I/O storage devices, a method for performing direct memory access (DMA) to the I/O storage devices comprising: providing a first channel control block (CCB) register in the I/O controller, said first CCB register storing a first CCB identifying DMA transfer parameters which specify an operation to be performed by the I/O controller; providing a chain status bit in the CCB, which when set, indicates to the I/O controller that another CCB is to be subsequently processed; providing an external memory address pointer which specifies an address, in an I/O storage device external to the I/O controller, of a subsequent CCB to be processed; performing operations specified by the CCB stored in the first CCB register; reading the chain status bit; if the chain status bit is set, upon completion of performing operations, retrieving a next CCB from the I/O storage device external to the I/O controller at the address specified by the external memory pointer; storing the next CCB in the first CCB register; incrementing the address in the external memory address pointer to point to a next CCB in the I/O storage device external to the I/O controller to be processed; and processing the next CCB stored in the first CCB register; whereby chaining of CCBs is achieved without increasing an amount of memory required in the I/O controller.
Claim 10
Dependent Claim
195 words
The method as set forth in claim 7, further comprising the steps of: providing a second CCB register in the I/O controller; providing a CCB register status bit to identify one of said first and second CCB registers as a CCB register containing a CCB currently being processed by the I/O controller; performing operations specified by the CCB located in the CCB register containing a CCB currently being processed; said step of storing the next CCB stores the next CCB in the other of said first and second CCB registers not currently being identified by the CCB register status bit; toggling the CCB register status bit to point to the CCB register not currently being identified by the CCB register status bit; whereby the CCB located in the CCB register not currently being identified by the CCB register status bit is processed after processing the CCB in the CCB register containing a CCB currently being processed and double buffering is performed by alternately storing subsequent CCBs in the first CCB register and the second CCB register and toggling the CCB register status bit to point to the CCB register containing a CCB currently being processed.
Claim 11
Dependent Claim
29 words
The method as set forth in claim 7, further comprising the step of restoring the first CCB processed in the first CCB register after processing of the last CCB.
Claim 12
Dependent Claim
67 words
The method as set forth in claim 9, wherein the step of restoring the first CCB comprises the steps of: initially storing the first CCB at a predetermined location in the I/O storage device external to the I/O controller; reading the first CCB from the predetermined location in the I/O storage device external to the I/O controller; and writing the first CCB in the first CCB register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-21 | 1998-05-23 | 1998-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-21 | 2002-05-23 | 2002-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-21 | 2006-05-23 | 2006-11-22 | $7700.00 | Window Closed / Lapsed |