Semiconductor memory device

Claim 1

A semiconductor memory device comprising: a memory cell array having a plurality of dynamic memory cell units, each of the memory cell units of said memory cell array including a first MOS transistor having first and second terminals, said first terminal of said first MOS transistor connected to a read data node; a second MOS transistor having first and second terminals, said first terminal of said second MOS transistor connected to said second terminal of said first MOS transistor; and first and second data storage capacitors respectively connected to said second terminals of said first and second MOS transistors; word lines respectively connected to gates of said first and second MOS transistors for supplying signals to control ON/OFF switching of said first and second MOS transistors; and register means arranged in a column portion of said memory cell array, for registering the data read from said memory cell units in a corresponding column in a time series manner.