Fast response matched filter receiver with decision feedback equalizer

Claim 2

A matched filter receiver in combination with a decision feedback equalizer, comprising: a transversal filter having a tapped delay line for receiving an incoming digital signal to produce successively delayed signals at successive taps of the delay line, a plurality of tap-weight multipliers connected respectively to the successive taps of said delay line, and means for summing output signals of said tap-weight multipliers to produce a filter output, and supplying the filter output to said decision feedback equalizer; a second tapped delay line having a series of delay elements for receiving said incoming digital signal to produce successively delayed signals at successive taps of the second delay line so that the delayed signal at a center tap of the second delay line is time coincident with an output signal from said decision feedback equalizer; a plurality of correlation circuits corresponding respectively to the tap-weight multipliers of said transversal filter and the successive taps of the second delay line, each of the correlation circuits comprising: a correlation detector for detecting a correlation between the output signal of said decision feedback equalizer and a signal from the corresponding tap of said second tapped delay line to produce a correlation output signal; integrator means for integrating said correlation output signal over a prescribed interval to produce an integrated signal; an adder having a first input terminal receiving said correlation output signal, and a second input terminal; delay means for delaying said correlation output signal for an interval equal to said prescribed interval to produce a delayed signal; a subtractor for detecting a difference between said delayed signal and an output signal of said adder to produce a difference signal and supplying the difference signal to the corresponding tap-weight multiplier; and means for initially coupling said integrated signal to the second input terminal of said adder and subsequently coupling said difference signal to said second input of the adder, instead of said integrated signal.

Claim 3

A matched filter receiver for a demodulator, comprising: a decision feedback equalizer; means for generating an out-of-sync signal when the demodulator is not synchronized with an incoming signal; a transversal filter having a tapped delay line for receiving a signal from said demodulator to produce successively delayed signals at successive taps of the delay line, a plurality of tap-weight multipliers connected respectively to the successive taps of said delay line, and means for summing output signals of said tap-weight multipliers to produce a filter output, and supplying the filter output to said decision feedback equalizer; a second tapped delay line having a series of delay elements connected to receive said incoming digital signal to produce successively delayed signals at successive taps of the second delay line so that the delayed signal at a center tap of the second delay line is time coincident with an output signal from said decision feedback equalizer; a plurality of correlation circuits corresponding respectively to the tap-weight multipliers of said transversal filter and the successive taps of the second delay line, each of the correlation circuits comprising: a correlation detector for detecting a correlation between the output signal of said decision feedback equalizer and a signal from the corresponding tap of said second tapped delay line to produce a correlation output signal; a resettable integrator, when enabled, for integrating said correlation output signal; an adder having a first input receiving an output signal from said correlation detector and a second input; delay means for delaying the output signal of said correlation detector for a prescribed interval; a subtractor for detecting a difference between output signals of said adder and said delay means to produce a difference signal and supplying the difference signal to the corresponding tap-weight multiplier; and control means responsive to said out-of-sync signal for resetting said integrator and responsive to absence of said out-of-sync signal for enabling said integrator to integrate said correlation output signal over an interval equal to said prescribed interval to produce an integrated signal, coupling said integrated signal to the second input of said adder, and subsequently coupling said difference signal to said second input of said adder, instead of said integrated signal.

Claim 4

A matched filter receiver for a demodulator, comprising: a decision feedback equalizer; means for generating an out-of-sync signal when the demodulator is not synchronized with an incoming signal; a transversal filter having a tapped delay line for receiving a signal from said demodulator to produce successively delayed signals at successive taps of the delay line, a plurality of tap-weight multipliers connected respectively to the successive taps of said delay line, and means for summing output signals of said tap-weight multipliers to produce a filter output, and supplying the filter output to said decision feedback equalizer; a second tapped delay line having a series of delay elements connected to receive said incoming digital signal to produce successively delayed signals at successive taps of the second delay line so that the delayed signal at a center tap of the second delay line is time coincident with an output signal from said decision feedback equalizer; a plurality of correlation circuits corresponding respectively to the tap-weight multipliers of said transversal filter and the successive taps of the second delay line, each of the correlation circuits comprising: a correlation detector for detecting a correlation between the output signal of said decision feedback equalizer and a signal from the corresponding tap of said second tapped delay line to produce a correlation output signal; a resettable integrator, when enabled, for integrating said correlation output signal; an adder having a first input receiving an output signal from said correlation detector and a second input; delay means for delaying the output signal of said correlation detector for a prescribed interval; a subtractor for detecting a difference between output signals of said adder and said delay means to produce a difference signal and supplying the difference signal to the corresponding tap-weight multiplier; and control means responsive to said out-of-sync signal for resetting said integrator and responsive to absence of said out-of-sync signal for enabling said integrator to integrate said correlation output signal over an interval equal to said prescribed interval to produce an integrated signal, coupling said integrated signal to the second input of said adder, and subsequently coupling said difference signal to said second input of said adder, instead of said integrated signal.

Claim 5

A matched filter receiver for a demodulator having means for generating an out-of-sync signal when the demodulator is not synchronized with an incoming signal, comprising: a decision feedback equalizer; a transversal filter having a tapped delay line for receiving an incoming digital signal to produce successively delayed signals at successive taps of the delay line, a plurality of tap-weight multipliers connected respectively to the successive taps of said delay line, and means for summing output signals of said tap-weight multipliers to produce a filter output, and supplying the filter output to said decision feedback equalizer; a second tapped delay line having a series of delay elements connected to receive said incoming digital signal to produce successively delayed signals at successive taps of the second delay line so that the delayed signal at a center tap of the second delay line is time coincident with an output signal from said decision feedback equalizer; a plurality of correlation circuits corresponding respectively to the tap-weight multipliers of said transversal filter and the successive taps of the second delay line, each of said correlation circuits comprising: a correlation detector for detecting a correlation between the output signal of said decision feedback equalizer and a signal from the corresponding tap of said second tapped-delay line; a resettable integrator, when enabled, for integrating a signal from said correlation detector; one-symbol delay means for delaying an output signal of said integrator for a symbol interval; a selector having a first input terminal connected to the output of said one-symbol delay means, a second input terminal, and an output terminal for selectively establishing a first connection between said first input terminal and said output terminal, or a second connection between said second input terminal and said output terminal; a resettable adder, when enabled, for summing output signals from said selector and said correlation detector; L-symbol delay means for delaying a signal from said correlation detector for an L-symbol interval; a resettable subtractor, when enabled, for subtracting the output of said L-symbol delay means from the output of said resettable adder to produce a difference signal and supplying the difference signal to the second input of said selector and to the corresponding tap-weight multiplier; first resetting means responsive to said out-of-sync signal for resetting said integrator and responsive to absence of said out-of-sync signal for enabling said integrator; second resetting means for resetting said resettable adder and subtractor an L -symbol interval after said integrator is reset by said first resetting means and enabling said resettable adder and resettable subtractor an L-symbol interval after said integrator is enabled; and control means for initially causing said selector to establish said first connection and subsequently causing said selector to establish said second connection an (L+1)-symbol interval after said integrator is enabled by said first resetting means.

Claim 6

A matched filter receiver for a demodulator having means for generating an out-of-sync signal when the demodulator is not synchronized with an incoming signal, comprising: a decision feedback equalizer; a transversal filter having a tapped delay line for receiving an incoming digital signal to produce successively delayed signals at successive taps of the delay line, a plurality of tap-weight multipliers connected respectively to the successive taps of said delay line, and means for summing output signals of said tap-weight multipliers to produce a filter output, and supplying the filter output to said decision feedback equalizer; a second tapped delay line having a series of delay elements connected to receive said incoming digital signal to produce successively delayed signals at successive taps of the second delay line so that the delayed signal at a center tap of the second delay line is time coincident with an output signal from said decision feedback equalizer; a plurality of correlation circuits corresponding respectively to the tap-weight multipliers of said transversal filter and the successive taps of the second delay line, each of said correlation circuits comprising: a correlation detector for detecting a correlation between the output signal of said decision feedback equalizer and a signal from the corresponding tap of said second tapped-delay line; a resettable integrator, when enabled, for integrating a signal from said correlation detector; one-symbol delay means for delaying an output signal of said integrator for a symbol interval; a selector having a first input terminal connected to the output of said one-symbol delay means, a second input terminal, and an output terminal for selectively establishing a first connection between said first input terminal and said output terminal, or a second connection between said second input terminal and said output terminal; a resettable adder, when enabled, for summing output signals from said selector and said correlation detector; L-symbol delay means for delaying a signal from said correlation detector for an L-symbol interval; a resettable subtractor, when enabled, for subtracting the output of said L-symbol delay means from the output of said resettable adder to produce a difference signal and supplying the difference signal to the second input of said selector and to the corresponding tap-weight multiplier; first resetting means responsive to said out-of-sync signal for resetting said integrator and responsive to absence of said out-of-sync signal for enabling said integrator; second resetting means for resetting said resettable adder and subtractor an L -symbol interval after said integrator is reset by said first resetting means and enabling said resettable adder and resettable subtractor an L-symbol interval after said integrator is enabled; and control means for initially causing said selector to establish said first connection and subsequently causing said selector to establish said second connection an (L+1)-symbol interval after said integrator is enabled by said first resetting means.