Method of making EEPROM array with buried N+ windows and with separate erasing and programming regions

Claim 1

A method of fabricating a nonvolatile memory cell at tile face c,f a semiconductor substrate of a first conductivity-type, comprising: creating at least two cell-isolation field insulator regions in said substrate, each said field insulator regions having at least one vertical edge with said vertical edges separated on said substrate by a channel-drain area, and each said field insulator region having a horizontal edge; creating a source-line segment adjacent each said horizontal edge to each said field insulator region by selectively implanting a dopant of a second conductivity-type opposite said first conductivity-type in said substrate; forming a line insulator over said each source-line segment; forming a tunnel-window insulator at a junction between one of said line insulators and said field insulator regions; forming a first conductive layer and an underlying gate insulator layer over said face of said substrate, including said field insulators and said line insulator; forming an inter-level insulator layer over said first conductive layer; selectively etching said second conductive layer and said inter-level insulator layer to define a floating-gate strip at least over said channel-drain area and said tunnel-window insulator; forming a second conductive layer over said substrate, including said floating-gate strip; stack etching said second conductive layer, said inter-level insulator layer and said first conductive layer, to define a control gate and a floating gate, said control gate and said floating gate each including a channel-section over at least a part of said channel-drain area, said floating gate including a tunnel-window section over said tunnel-window insulator; and using said control gate as an implant mask, selectively implanting a dopant of a said second conductivity-type to create a source region and to create a drain region in areas of said substrate not covered by said field insulators and line insulators.

Claim 2

A method of fabricating a nonvolatile memory cell at tile face c,f a semiconductor substrate of a first conductivity-type, comprising: creating at least two cell-isolation field insulator regions in said substrate, each said field insulator regions having at least one vertical edge with said vertical edges separated on said substrate by a channel-drain area, and each said field insulator region having a horizontal edge; creating a source-line segment adjacent each said horizontal edge to each said field insulator region by selectively implanting a dopant of a second conductivity-type opposite said first conductivity-type in said substrate; forming a line insulator over said each source-line segment; forming a tunnel-window insulator at a junction between one of said line insulators and said field insulator regions; forming a first conductive layer and an underlying gate insulator layer over said face of said substrate, including said field insulators and said line insulator; forming an inter-level insulator layer over said first conductive layer; selectively etching said second conductive layer and said inter-level insulator layer to define a floating-gate strip at least over said channel-drain area and said tunnel-window insulator; forming a second conductive layer over said substrate, including said floating-gate strip; stack etching said second conductive layer, said inter-level insulator layer and said first conductive layer, to define a control gate and a floating gate, said control gate and said floating gate each including a channel-section over at least a part of said channel-drain area, said floating gate including a tunnel-window section over said tunnel-window insulator; and using said control gate as an implant mask, selectively implanting a dopant of a said second conductivity-type to create a source region and to create a drain region in areas of said substrate not covered by said field insulators and line insulators.

Claim 8

A method of fabricating a nonvolatile memory cell array at the face of a semiconductor layer having a first conductivity-type, comprising: forming rows and columns of cell-isolation field insulator regions each said field insulator having a pair, or row, edges and a pair of column edges, each of said column edges separated on said substrate by a channel-drain area; implanting a dopant of a second conductivity-type opposite said first conductivity-type to create source-line segments in said substrate, said source-line segments extending from a row edge of one said field insulator region to a row edge of an adjacent field insulator region; forming line insulators over said source-line segments; forming tunnel-window insulators at the junction of each said field insulator region and each said line insulator; forming floating-gate strips from a deposited conductive layer, said floating gate strips at least over said channel-drain area and over said tunnel-window insulators, said floating-gate strips insulated from said substrate by gate-insulator layers and having inter-level insulator layers over said floating-gate strips; forming control gates and wordlines from a deposited conductive layer over said inter-level insulator layers and, at the same time, forming floating gates from said floating gate strips, each said control gate and each said floating gate extending over at least a part of a said channel-drain area and extending over a said tunnel-window insulator; using said control gates as masks, implanting a dopant of a said second conductivity type opposite said first type to create source regions and to create drain regions in areas of said substrate other than said field insulator regions and line insulators; and forming drain lines connecting columns of said drain regions.

Claim 9

A method of fabricating a nonvolatile memory cell array at the face of a semiconductor layer having a first conductivity-type, comprising: forming rows and columns of cell-isolation field insulator regions each said field insulator having a pair, or row, edges and a pair of column edges, each of said column edges separated on said substrate by a channel-drain area; implanting a dopant of a second conductivity-type opposite said first conductivity-type to create source-line segments in said substrate, said source-line segments extending from a row edge of one said field insulator region to a row edge of an adjacent field insulator region; forming line insulators over said source-line segments; forming tunnel-window insulators at the junction of each said field insulator region and each said line insulator; forming floating-gate strips from a deposited conductive layer, said floating gate strips at least over said channel-drain area and over said tunnel-window insulators, said floating-gate strips insulated from said substrate by gate-insulator layers and having inter-level insulator layers over said floating-gate strips; forming control gates and wordlines from a deposited conductive layer over said inter-level insulator layers and, at the same time, forming floating gates from said floating gate strips, each said control gate and each said floating gate extending over at least a part of a said channel-drain area and extending over a said tunnel-window insulator; using said control gates as masks, implanting a dopant of a said second conductivity type opposite said first type to create source regions and to create drain regions in areas of said substrate other than said field insulator regions and line insulators; and forming drain lines connecting columns of said drain regions.