Method and apparatus for controlling operation of a cache memory during an interrupt

Claim 2

A data processing system comprising: main memory means for storing information therein at relatively low speed; cache memory means for storing information therein at relatively high speed; means for generating a hardware interrupt signal in response to a hardware interrupt; and processing means for performing data processing tasks, said processing means being operatively connected to said main memory means and said cache memory means, said processing means including hardware interrupt responsive cache controlling means, responsive to said hardware interrupt signal, for controlling said cache memory means to perform a first data processing task, and to suspend performance of said first data processing task and perform a second data processing task in response to said hardware interrupt signal, and for controlling information storing in at least part of said cache memory means during said second data processing task which is performed in response to said hardware interrupt signal, to prevent said part of said cache memory means from being disturbed during performance of said second data processing task in response to said hardware interrupt signal.

Claim 3

The data processing system of claim 1 wherein said interrupt responsive cache controlling means comprises: a program status word, associated with said second task, said program status word including cache control information therein; a program status word register for storing therein said program status word including said cache control information; wherein said hardware interrupt responsive cache controlling means is responsive to said cache control information in said program status word register, for controlling information storing in said part of said cache memory means during performance of said second data processing task.

Claim 4

The data processing system of claim 1 wherein said processing means further includes arithmetic and logic means and wherein hardware interrupt responsive cache controlling means comprises: interrupt controlling means for controlling said arithmetic and logic means to perform said first data processing task and to suspend performance of said first data processing task and perform a second data processing task in response to said interrupt signal; and cache controlling means, responsive to said interrupt controlling means, for controlling information storing in at least part of said cache memory means during said second data processing task which is performed in response to said hardware interrupt signal, to thereby prevent said part of said cache memory means from being disturbed during performance of said second data processing task in response to said hardware interrupt signal.

Claim 5

The data processing system of claim 3 wherein said cache controlling means comprises means for selectively preventing storing of data in said cache memory means.

Claim 6

The data processing system of claim 3 wherein said cache controlling means comprises means for selectively preventing storing of instructions in said cache memory means.

Claim 7

The data processing system of claim 3 wherein said cache controlling means comprises means for selectively preventing storing of instructions and data in said cache memory means.

Claim 8

The data processing system of claim 3 wherein said cache controlling means comprises means for selectively preventing overwriting of data in said cache memory means.

Claim 9

The data processing system of claim 3 wherein said cache controlling means comprises means for selectively preventing overwriting of instructions in said cache memory means.

Claim 10

The data processing system of claim 3 wherein said cache controlling means comprises means for selectively preventing overwriting of instructions and data in said cache memory means.

Claim 11

A cache control method for a data processing system which generates a hardware interrupt signal in response to a hardware interrupt, said data processing system including main memory for storing information therein at relatively low speed, and cache memory for storing information therein at relatively high speed, said cache control method comprising the steps of: performing a first data processing task; receiving a hardware interrupt signal; interrupting performance of the first data processing task to perform a second data processing task in response to the received hardware interrupt signal; preventing at least part of the cache memory from being disturbed during performance of the second data processing task; and resuming performance of the first data processing task after performing the second data processing task; whereby part of the cache memory is undisturbed when performance of the first data processing task resumes.

Claim 12

A cache control method for a data processing system which generates a hardware interrupt signal in response to a hardware interrupt, said data processing system including main memory for storing information therein at relatively low speed, and cache memory for storing information therein at relatively high speed, said cache control method comprising the steps of: performing a first data processing task; receiving a hardware interrupt signal; interrupting performance of the first data processing task to perform a second data processing task in response to the received hardware interrupt signal; preventing at least part of the cache memory from being disturbed during performance of the second data processing task; and resuming performance of the first data processing task after performing the second data processing task; whereby part of the cache memory is undisturbed when performance of the first data processing task resumes.

Claim 13

The cache control method of claim 10 wherein said preventing step comprises the step of preventing storing of data in the cache memory during performance of the second data processing task.

Claim 14

The cache control method of claim 10 wherein said preventing step comprises the step of preventing storing of instructions in the cache memory during performance of the second data processing task.

Claim 15

The cache control method of claim 10 wherein said preventing step comprises the step of preventing storing of instructions and data in the cache memory during performance of the second data processing task.

Claim 16

The cache control method of claim 10 wherein said preventing step comprises the step of preventing overwriting of data in the cache memory during performance of the second data processing task.

Claim 17

The cache control method of claim 10 wherein said preventing step comprises the step of preventing overwriting of instructions in the cache memory during performance of the second data processing task.

Claim 18

The cache control method of claim 10 wherein said preventing step comprises the step of preventing overwriting of instructions and data in the cache memory during performance of the second data processing task.

Claim 19

The cache control method of claim 10: wherein said performing step comprises the step of loading a first program status word, including cache control data, into a program status register; wherein said interrupting step comprises the step of loading a second program status word, including cache control data, into the program status register; wherein said preventing step comprises the step of controlling operation of the cache memory according to the cache control data in the second program status word; and wherein said resuming step comprises the step of reloading the first program status word into the program status register.

Claim 20

The cache control method of claim 10: wherein said performing step comprises the step of loading a first program status vector, including cache control data, into a program status vector register; wherein said interrupting step comprises the step of loading a second program status vector, including cache control data, into the program status vector register; wherein said preventing step comprises the step of controlling operation of the cache memory according to the cache control data in the second program status vector; and wherein said resuming step comprises the step of reloading the first program status vector into the program status vector register.

Claim 21

A cache control method for a data processing system including main memory for storing information therein at relatively low speed, and cache memory for storing information therein at relatively high speed, said cache control method comprising the steps of: performing a first data processing task; receiving an interrupt signal; interrupting performance of the first data processing task to perform a second data processing task in response to the received interrupt signal; preventing at least part of the cache memory from being disturbed during performance of the second data processing task; and resuming performance of the first data processing task after performing the second data processing task; wherein said performing step is preceded by the step of loading a plurality of program status words, each including cache control data, into a program status register; wherein said performing step comprises the step of performing the first data processing task according to the information in a first one of the program status words; wherein said interrupting step comprises the step of performing the second data processing task according to the information in a second one of the program status words; wherein said preventing step comprises the step of controlling operation of the cache memory according to the cache control data in the second program status word; and wherein said resuming step comprises the step of resuming performance of the first data processing task according to the information in the first program status word; whereby part of the cache memory is undisturbed when performance of the first data processing task resumes.

Claim 22

A cache control method for a data processing system including main memory for storing information therein at relatively low speed, and cache memory for storing information therein at relatively high speed, said cache control method comprising the steps of: performing a first data processing task; receiving an interrupt signal; interrupting performance of the first data processing task to perform a second data processing task in response to the received interrupt signal; preventing at least part of the cache memory from being disturbed during performance of the second data processing task; and resuming performance of the first data processing task after performing the second data processing task; wherein said performing step is preceded by the step of loading a plurality of program status words, each including cache control data, into a program status register; wherein said performing step comprises the step of performing the first data processing task according to the information in a first one of the program status words; wherein said interrupting step comprises the step of performing the second data processing task according to the information in a second one of the program status words; wherein said preventing step comprises the step of controlling operation of the cache memory according to the cache control data in the second program status word; and wherein said resuming step comprises the step of resuming performance of the first data processing task according to the information in the first program status word; whereby part of the cache memory is undisturbed when performance of the first data processing task resumes.

Claim 23

A data processing system comprising: main memory means for storing information therein at relatively low speed; cache memory means for storing information therein at relatively high speed; arithmetic and logic means operatively connected to said main memory means and said cache memory means; program status word storing means, for storing therein a program status word including status data and cache control data, corresponding to the status of a program during an interrupt; interrupt controlling means operatively connected to said arithmetic and logic means and to said program status word storing means, for controlling operation of said arithmetic and logic means in response to said status data during an interrupt; and cache controlling means, operatively connected to said cache memory means and to said program status word storing means, for controlling information storing in said cache memory means in response to said cache control data during an interrupt; wherein said program status word storing means comprises a program status vector register for storing a plurality of program status words therein, each of which is associated with a predetermined interrupt level, and each of which includes status data and cache control data for the associated interrupt level; wherein said interrupt controlling means is responsive to an interrupt at one of said predetermined interrupt levels, for controlling said arithmetic and logic means in response to the status data for the associated interrupt level; and wherein said cache controlling means controls information storing in said cache memory means in response to the cache control data for the associated interrupt level; whereby information storing in said cache memory means is selectively controlled during an interrupt in response to the contents of said program status word storing means.

Claim 24

A data processing system comprising: main memory means for storing information therein at relatively low speed; cache memory means for storing information therein at relatively high speed; arithmetic and logic means operatively connected to said main memory means and said cache memory means; program status word storing means, for storing therein a program status word including status data and cache control data, corresponding to the status of a program during an interrupt; interrupt controlling means operatively connected to said arithmetic and logic means and to said program status word storing means, for controlling operation of said arithmetic and logic means in response to said status data during an interrupt; and cache controlling means, operatively connected to said cache memory means and to said program status word storing means, for controlling information storing in said cache memory means in response to said cache control data during an interrupt; wherein said program status word storing means comprises a program status vector register for storing a plurality of program status words therein, each of which is associated with a predetermined interrupt level, and each of which includes status data and cache control data for the associated interrupt level; wherein said interrupt controlling means is responsive to an interrupt at one of said predetermined interrupt levels, for controlling said arithmetic and logic means in response to the status data for the associated interrupt level; and wherein said cache controlling means controls information storing in said cache memory means in response to the cache control data for the associated interrupt level; whereby information storing in said cache memory means is selectively controlled during an interrupt in response to the contents of said program status word storing means.

Claim 25

A data processing system comprising: main memory means for storing information therein at relatively low speed; cache memory means for storing information therein at relatively high speed; arithmetic and logic means operatively connected to said main memory means and said cache memory means; program status word storing means, for storing therein a program status word including status data and cache control data, corresponding to the status of a program during an interrupt; interrupt controlling means operatively connected to said arithmetic and logic means and to said program status word storing means, for controlling operation of said arithmetic and logic means in response to said status data during an interrupt; and cache controlling means, operatively connected to said cache memory means and to said program status word storing means, for controlling information storing in said cache memory means in response to said cache control data during an interrupt; wherein said data processing system comprises a multiple virtual machine data processing system; wherein said program status word storing means comprises program status vector register, for storing a plurality of program status words therein, each of which is associated with a predetermined interrupt level, and each of which includes status data and cache control data for the associated interrupt level; wherein said interrupt controlling means is responsive to an interrupt at one of said predetermined interrupt levels and for one of said multiple virtual machines, for storing a program status vector for said one virtual machine in said program status vector register, and for controlling said arithmetic and logic means in response to the status data for the associated interrupt level in said program status vector register; and wherein said cache controlling means controls information storing in said cache memory means in response to the associated cache control data; whereby information storing in said cache memory means is selectively controlled during an interrupt in response to the contents of said program status word strong means.

Claim 26

A data processing system comprising: main memory means for storing information therein at relatively low speed; cache memory means for storing information therein at relatively high speed; arithmetic and logic means operatively connected to said main memory means and said cache memory means; program status word storing means, for storing therein a program status word including status data and cache control data, corresponding to the status of a program during an interrupt; interrupt controlling means operatively connected to said arithmetic and logic means and to said program status word storing means, for controlling operation of said arithmetic and logic means in response to said status data during an interrupt; and cache controlling means, operatively connected to said cache memory means and to said program status word storing means, for controlling information storing in said cache memory means in response to said cache control data during an interrupt; wherein said data processing system comprises a multiple virtual machine data processing system; wherein said program status word storing means comprises program status vector register, for storing a plurality of program status words therein, each of which is associated with a predetermined interrupt level, and each of which includes status data and cache control data for the associated interrupt level; wherein said interrupt controlling means is responsive to an interrupt at one of said predetermined interrupt levels and for one of said multiple virtual machines, for storing a program status vector for said one virtual machine in said program status vector register, and for controlling said arithmetic and logic means in response to the status data for the associated interrupt level in said program status vector register; and wherein said cache controlling means controls information storing in said cache memory means in response to the associated cache control data; whereby information storing in said cache memory means is selectively controlled during an interrupt in response to the contents of said program status word strong means.

Claim 27

The data processing system of claim 20 wherein said cache control data comprises data for selectively preventing storing of data in said cache memory means.

Claim 28

The data processing system of claim 21 wherein said cache control data comprises data for selectively preventing storing of instructions in said cache memory means.

Claim 29

The data processing system of claim 20 wherein said cache control data comprises data for selectively preventing storing of instructions and data in said cache memory means.

Claim 30

The data processing system of claim 21 wherein said cache control data comprises data for selectively preventing overwriting of data in said cache memory means.

Claim 31

The data processing system of claim 20 wherein said cache control data comprises data for selectively preventing overwriting of instructions in said cache memory means.

Claim 32

The data processing system of claim 21 wherein said cache control data comprises data for selectively preventing overwriting of instructions and data in said cache memory means.