US5371877A — Apparatus for alternatively accessing single port…

Claim 1

Independent Claim 271 words

A circuit for accessing information, said circuit comprising: a clock supplying a clock signal having a first phase and a second phase; a first bank of single port random access memory that is accessed for reading during said first phase; a second bank of single port random access memory that is accessed for reading during said second phase; read circuitry, coupled to said first bank and to said second bank, sequentially reading every other piece of sequential data from an alternate one of said first bank of memory or said second bank of memory during said first and second clock phases, respectively; write circuitry writing data into said first bank of memory during said second phase and also writing data into said second bank of memory during said first phase, wherein at least one piece of data may be written to said first bank or to said second bank while an other bank is being read by said read circuitry; and recovery circuitry supplying data in response to removal of a hold condition, said recovery circuitry comprising: first address generation circuitry generating a first address in a given clock cycle for addressing said first bank or said second bank; second address generation circuitry generating a second address in said given clock cycle for addressing said first bank or said second bank wherein said second address is equal to an address succeeding said first address; delay storage circuitry delaying data output from said first bank and said second bank by one clock cycle; and multiplexing circuitry supplying information to output terminals from either said read circuitry or from said delay storage circuitry.

Claim 2

Dependent Claim 271 words

A circuit for accessing information, said circuit comprising: a clock supplying a clock signal having a first phase and a second phase; a first bank of single port random access memory that is accessed for reading during said first phase; a second bank of single port random access memory that is accessed for reading during said second phase; read circuitry, coupled to said first bank and to said second bank, sequentially reading every other piece of sequential data from an alternate one of said first bank of memory or said second bank of memory during said first and second clock phases, respectively; write circuitry writing data into said first bank of memory during said second phase and also writing data into said second bank of memory during said first phase, wherein at least one piece of data may be written to said first bank or to said second bank while an other bank is being read by said read circuitry; and recovery circuitry supplying data in response to removal of a hold condition, said recovery circuitry comprising: first address generation circuitry generating a first address in a given clock cycle for addressing said first bank or said second bank; second address generation circuitry generating a second address in said given clock cycle for addressing said first bank or said second bank wherein said second address is equal to an address succeeding said first address; delay storage circuitry delaying data output from said first bank and said second bank by one clock cycle; and multiplexing circuitry supplying information to output terminals from either said read circuitry or from said delay storage circuitry.

Claim 3

Dependent Claim 31 words

The circuit as described in claim 1 wherein said delay storage circuitry stores a maximum of one piece of data in response to a hold condition of N cycles in duration.

Claim 4

Dependent Claim 66 words

The circuit as described in claim 1 wherein, provided said hold condition is removed during said first phase of said clock signal, said multiplexing circuitry supplies said information from said delay storage circuit and wherein said first bank of memory and said second bank of memory are addressed by said second address and wherein further said data is delayed before being supplied to said output terminals.

Claim 5

Dependent Claim 55 words

The circuit as claimed in claim 3 wherein, provided said hold condition is removed during said second phase of said clock signal, said first bank of memory and said second bank of memory supply said data and wherein said first bank of memory and said second bank of memory are addressed by said first address.

Claim 6

Independent Claim 253 words

A method of accessing information, said method comprising the steps of: (a) generating a clock signal having a first phase and a second phase; (b) sequentially reading every other piece of sequential data from an alternate one of a first bank of single port random access memory during said first phase or a second bank of single port random access memory during said second clock phase; (c) writing nonsequential data into said first bank of memory during said second phase and writing nonsequential data into said second bank of memory during said first phase, wherein at least one piece of nonsequential data may be written to said first bank or to said second bank while an other bank is being read by said step (b) of sequentially reading; and (d) supplying data to output terminals in response to removal of a hold condition, said step of supplying data comprising the steps of: (1) generating a first address in a given clock cycle for addressing said first bank or said second bank; (2) generating a second address in said given clock cycle for addressing said first bank or said second bank wherein said second address is equal to an address succeeding said first address; (3) delaying data output from said first bank and said second bank by one clock cycle by storing said data output from step (b) into a delay storage; and (4) outputting said data to said output terminals from either said step (b) of sequentially reading or from said delay storage.

Claim 7

Independent Claim 253 words

A method of accessing information, said method comprising the steps of: (a) generating a clock signal having a first phase and a second phase; (b) sequentially reading every other piece of sequential data from an alternate one of a first bank of single port random access memory during said first phase or a second bank of single port random access memory during said second clock phase; (c) writing nonsequential data into said first bank of memory during said second phase and writing nonsequential data into said second bank of memory during said first phase, wherein at least one piece of nonsequential data may be written to said first bank or to said second bank while an other bank is being read by said step (b) of sequentially reading; and (d) supplying data to output terminals in response to removal of a hold condition, said step of supplying data comprising the steps of: (1) generating a first address in a given clock cycle for addressing said first bank or said second bank; (2) generating a second address in said given clock cycle for addressing said first bank or said second bank wherein said second address is equal to an address succeeding said first address; (3) delaying data output from said first bank and said second bank by one clock cycle by storing said data output from step (b) into a delay storage; and (4) outputting said data to said output terminals from either said step (b) of sequentially reading or from said delay storage.

Claim 8

Dependent Claim 29 words

The method as described in claim 5 wherein said delay storage contains a maximum of one data piece in response to a hold condition of N cycles in duration.

Claim 9

Dependent Claim 72 words

The method as described in claim 5 wherein, provided said hold condition is removed during said first phase of said clock signal, then said step (d)(4) of outputting said data to said output terminals outputs said data from said delay storage, and further comprising the step of addressing said first bank of memory and said second bank of memory by said second address and wherein said data is delayed before being output.

Claim 10

Dependent Claim 67 words

The method as described in claim 7 wherein, provided said hold condition is removed during said second phase of said clock signal, then said step (d)(4) of outputting said data to said output terminals outputs said data directly from said step (b) of sequentially reading, and further comprising the step of addressing said first bank of memory and said second bank of memory by said first address.

Claim 11

Dependent Claim 215 words

A circuit for accessing information, said circuit comprising: a clock supplying a clock signal having a first phase and a second phase; a first bank of single port random access memory accessed for reading during said first phase; a second bank of single port random access memory accessed for reading during said second phase; read circuitry coupled to said first bank and to said second bank sequentially reading every other piece of sequential data from an alternate one of said first bank of memory or said second bank of memory during said first and second clock phases, respectively; write circuitry writing data into said first bank of memory during said second phase and also writing data into said second bank of memory during said first phase; and recovery circuitry supplying data in response to removal of a hold condition, said recovery circuitry comprising: first address generation circuitry generating a first address within a given clock cycle for addressing said first bank or said second bank; second address generation circuitry generating a second address within said given clock cycle for addressing said first bank or said second bank wherein said second address is equal to an address succeeding said first address; and delay storage circuitry delaying data output from said first bank and said second bank.

Claim 12

Dependent Claim 215 words

A circuit for accessing information, said circuit comprising: a clock supplying a clock signal having a first phase and a second phase; a first bank of single port random access memory accessed for reading during said first phase; a second bank of single port random access memory accessed for reading during said second phase; read circuitry coupled to said first bank and to said second bank sequentially reading every other piece of sequential data from an alternate one of said first bank of memory or said second bank of memory during said first and second clock phases, respectively; write circuitry writing data into said first bank of memory during said second phase and also writing data into said second bank of memory during said first phase; and recovery circuitry supplying data in response to removal of a hold condition, said recovery circuitry comprising: first address generation circuitry generating a first address within a given clock cycle for addressing said first bank or said second bank; second address generation circuitry generating a second address within said given clock cycle for addressing said first bank or said second bank wherein said second address is equal to an address succeeding said first address; and delay storage circuitry delaying data output from said first bank and said second bank.

Claim 13

Dependent Claim 59 words

The circuit as described in claim 9 wherein said delay storage circuit stores a maximum of one data piece in response to a hold condition of N cycles in duration and wherein said recovery circuitry supplies said data with a maximum of one cycle of delay subsequent to said removal of said hold condition of N cycles in duration.

Claim 14

Dependent Claim 32 words

The circuit as described in claim 9 wherein said delay storage circuit stores a maximum of one data piece in response to a hold condition of at least 2 cycles in duration.

Claim 15

Dependent Claim 41 words

The circuit as described in claim 9 wherein at least one piece of data may be written to said first bank or to said second bank by said write circuitry while an other bank is being read by said read circuitry.

Claim 16

Dependent Claim 56 words

The circuit as described in claim 12 wherein, provided said hold condition is removed during said first phase, said delay storage circuit supplies data to output terminals and wherein further said first bank of memory and said second bank of memory are addressed by said second address and wherein said data is delayed before being supplied.

Claim 17

Dependent Claim 57 words

The circuit as described in claim 13 wherein, provided said hold condition is removed during said second phase, said first bank of memory and said second bank of memory directly supply said data to said output terminals and wherein further said first bank of memory and said second bank of memory are addressed by said first address.

Claim 18

Dependent Claim 188 words

A circuit for providing a function of a dual port FIFO circuit comprising a first bank of single port random access memory, a second bank of single port random access memory, means for sequentially writing every other piece of sequential data to an alternate one of the first and second banks of memory during first and second clock phase signals, respectively, means for reading data first stored in the first and second bank of memory which is not being written during a period in which data is being written to the first and second bank of memory which is being written, and recovery means for supplying data in response to removal of a hold condition said recovery means comprising: means for generating a first address within a given clock cycle for addressing said first bank and said second bank, means for generating a second address within said given clock cycle for addressing said first bank and said second bank wherein said second address is equal to an addresses succeeding said first address, and delay storage means for delaying data output from said first bank and said second bank.

Claim 19

Dependent Claim 188 words

A circuit for providing a function of a dual port FIFO circuit comprising a first bank of single port random access memory, a second bank of single port random access memory, means for sequentially writing every other piece of sequential data to an alternate one of the first and second banks of memory during first and second clock phase signals, respectively, means for reading data first stored in the first and second bank of memory which is not being written during a period in which data is being written to the first and second bank of memory which is being written, and recovery means for supplying data in response to removal of a hold condition said recovery means comprising: means for generating a first address within a given clock cycle for addressing said first bank and said second bank, means for generating a second address within said given clock cycle for addressing said first bank and said second bank wherein said second address is equal to an addresses succeeding said first address, and delay storage means for delaying data output from said first bank and said second bank.

Claim 20

Dependent Claim 42 words

The circuit for providing the function of a dual port FIFO circuit as claimed in claim 15 further comprising means for furnishing to the output terminals data read from the first and second bank of memory or from the delay storage means.

Claim 21

Dependent Claim 60 words

The circuit for providing the function of a dual port FIFO circuit as claimed in claim 16 wherein, provided said hold condition is removed during said first clock phase signal, said means for furnishing supplies data to output terminals from said delay storage means and wherein further said first and second banks of memory are addressed by said second address.

Claim 22

Dependent Claim 63 words

The circuit for providing the function of a dual port FIFO circuit as claimed in claim 17 wherein, provided said hold condition is removed during said second phase, said means for furnishing supplies data to said output terminals directly from said first and second banks of memory and wherein further said first and second banks of memory are addressed by said first address.

Claim 23

Dependent Claim 57 words

The circuit for providing the function of a dual port FIFO circuit as claimed in claim 17 in which the means for furnishing to the output terminals data read from one of the first and the second banks of memory or from the delay storage means allows data to be furnished on a one clock cycle delay.

Claim 24

Dependent Claim 76 words

The circuit for providing the function of a dual port FIFO circuit as claimed in claim 19 in which the means for furnishing to the output terminals data read from the first and second bank of memory or from the delay storage means furnishes data from the other of either the first and second bank of memory or from the delay storage means whenever a destination for data cannot use the data during that clock period.

Claim 25

Dependent Claim 93 words

The circuit for providing the function of a dual port FIFO circuit as claimed in claim 17 in which the means for sequentially writing every other piece of sequential data to an alternate one of the first and second banks of memory comprises means for generating the first and second phase signals during succeeding clock periods, means for inverting the first and second phase signals, and means for using the signals generated and the inverted signals to enable either the first or the second bank of memory for writing during each clock period.

Claim 26

Dependent Claim 89 words

The circuit for providing the function of a dual port FIFO circuit as claimed in claim 21 in which the means for reading data first stored in the first and second bank of memory which is not being written during a period in which data is being written to the first and second bank of memory which is being written comprises means for utilizing the first and second phase signals to enable the first or the second bank of memory not being used for writing during each clock period.

Claim 27

Dependent Claim 83 words

The circuit for providing the function of a dual port FIFO circuit as claimed in claim 22 in which the means for sequentially writing every other piece of sequential data to an alternate one of the first and second banks of memory further comprises means for providing addresses for reading and writing data, and means for utilizing the first and second phase signals to select a write address for the first or the second bank of memory to which data is being written.

Claim 28

Dependent Claim 83 words

The circuit for providing the function of a dual port FIFO circuit as claimed in claim 21 in which the means for sequentially writing every other piece of sequential data to an alternate one of the first and second banks of memory further comprises means for providing addresses for reading and writing data, and means for utilizing the first and second phase signals to select a write address for the first or the second bank of memory to which data is being written.

Claim 29

Dependent Claim 91 words

The circuit for providing the function of a dual port FIFO circuit as claimed in claim 24 in which the means for reading data first stored in the first and second banks of memory which is not being written during a period in which data is being written to the first and second bank of memory which is being written further comprises means for utilizing the first and second phase signals to select a read address for the first or the second bank of memory from which data is being read.

Claim 30

Dependent Claim 101 words

The circuit for providing the function of a dual port FIFO circuit as claimed in claim 25 in which the means for reading data first stored in the first and second banks of memory which is not being written during a period in which data is being written to the first and second bank of memory which is being written further comprises means for gating output signals from the first and second banks of memory, and means for utilizing the first and second phase signals to select the first or the second bank of memory from which data is being read.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1997-12-05	1998-06-06	1998-12-06	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2001-12-05	2002-06-06	2002-12-06	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2005-12-05	2006-06-06	2006-12-06	$7700.00	Window Closed / Lapsed

Apparatus for alternatively accessing single port random access memories to implement dual port first-in first-out memory

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