US5374583A
Expired / Lapsed
US
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Technology for local oxidation of silicon
Assignee: United Microelectronics Corp
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Filing: 1994-05-24
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Granted: 1994-12-20
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Expires: 2014-05-24
Abstract
Abstract A new method of local oxidation by means of forming a plurality of silicon trenches is described. Portions of the insulating layer over the surface of a silicon substrate not covered by a mask pattern are etched through exposing the portion of the silicon substrate that will form the device isolation region. A first trench is etched into the exposed portion of the substrate. A layer of silicon nitride is deposited over the insulating layer and within the trench. A layer of an aluminum-silicon alloy is deposited overlying the silicon nitride layer. The aluminum-silicon layer is etched away whereby silicon nodules are formed on the surface of the silicon nitride layer. The nodules are oxidized to form silicon dioxide nodules. Using the silicon dioxide nodules as a mask, the silicon nitride layer is etched through to the insulating layer where it exists and to the silicon substrate surface where it is exposed and a set of narrow trenches is etched into the exposed portions of the substrate. The silicon substrate within the set of trenches is oxidized wherein the silicon is transformed to silicon dioxide and the silicon dioxide expands to fill the set of trenches. The silicon nitride layer and the silicon dioxide nodules within the opening are pushed up to align with the silicon nitride layer and the silicon dioxide nodules on either side of the opening. The remaining insulating layer and silicon nitride layer are removed wherein the silicon dioxide nodules are also removed completing the device isolation of the IC.
Inventors
- 👤 Water Lur
- 👤 Jiun Y. Wu
- 👤 Anna Su
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:19
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/61; H10P50/00; H10P50/73; H10P76/00; H10P76/40; H10P76/408; H10P76/4085; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/0123; H10W10/10; H10W10/13; Y; Y10; Y10S; Y10S148/00; Y10S148/05
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
308 words
The method of forming a device isolation region of an integrated circuit by means of a plurality of silicon trenches comprising: providing an insulating layer over the surface of a silicon substrate; etching through portions of said insulating layer not covered by a mask pattern to said silicon substrate so as to provide an opening exposing the portion of said silicon substrate that will form the said device isolation region; etching a first trench into said exposed portion of said silicon substrate; depositing a layer of silicon nitride over said insulating layer and within said first trench in said silicon substrate; depositing a layer of an aluminum-silicon alloy overlying said silicon nitride layer; etching away said aluminum, silicon layer whereby silicon nodules are formed on the surface of said silicon nitride layer; oxidizing said silicon nodules to form silicon dioxide nodules; etching through said silicon nitride layer to said insulating layer where it exists and to said silicon substrate surface where said substrate is exposed within said opening using said silicon dioxide nodules as a mask; etching a set of narrow trenches into said exposed portions of said silicon substrate within said opening using said silicon dioxide nodules as a mask; selectively ion implanting channel-stops through said opening into said substrate underneath said set of trenches; oxidizing said silicon substrate within said set of trenches wherein said silicon substrate is transformed to silicon dioxide and wherein said silicon dioxide expands to fill said set of trenches and whereby said silicon nitride layer and said silicon dioxide nodules within said opening are pushed up to align with said silicon nitride layer and said silicon dioxide nodules on either side of said opening; and removing remaining said insulating layer and said silicon nitride layer wherein said silicon dioxide nodules are also removed completing said device isolation of said integrated circuit.
Claim 2
Independent Claim
308 words
The method of forming a device isolation region of an integrated circuit by means of a plurality of silicon trenches comprising: providing an insulating layer over the surface of a silicon substrate; etching through portions of said insulating layer not covered by a mask pattern to said silicon substrate so as to provide an opening exposing the portion of said silicon substrate that will form the said device isolation region; etching a first trench into said exposed portion of said silicon substrate; depositing a layer of silicon nitride over said insulating layer and within said first trench in said silicon substrate; depositing a layer of an aluminum-silicon alloy overlying said silicon nitride layer; etching away said aluminum, silicon layer whereby silicon nodules are formed on the surface of said silicon nitride layer; oxidizing said silicon nodules to form silicon dioxide nodules; etching through said silicon nitride layer to said insulating layer where it exists and to said silicon substrate surface where said substrate is exposed within said opening using said silicon dioxide nodules as a mask; etching a set of narrow trenches into said exposed portions of said silicon substrate within said opening using said silicon dioxide nodules as a mask; selectively ion implanting channel-stops through said opening into said substrate underneath said set of trenches; oxidizing said silicon substrate within said set of trenches wherein said silicon substrate is transformed to silicon dioxide and wherein said silicon dioxide expands to fill said set of trenches and whereby said silicon nitride layer and said silicon dioxide nodules within said opening are pushed up to align with said silicon nitride layer and said silicon dioxide nodules on either side of said opening; and removing remaining said insulating layer and said silicon nitride layer wherein said silicon dioxide nodules are also removed completing said device isolation of said integrated circuit.
Claim 3
Dependent Claim
27 words
The method of claim 1 wherein said first insulating layer is composed of silicon dioxide and has a preferred thickness of between about 500 to 1000 Angstroms.
Claim 4
Dependent Claim
21 words
The method of claim 1 wherein said first trench is etched to a depth of between about 1000 to 2000 Angstroms.
Claim 5
Dependent Claim
21 words
The method of claim 1 wherein said silicon nitride layer has a preferred thickness of between about 500 to 2000 Angstroms.
Claim 6
Dependent Claim
39 words
The method of claim 1 wherein said aluminum-silicon alloy layer is composed of between about 1 to 4% silicon and is deposited at greater than about 400° C. to a preferred thickness of between about 5000 to 20,000 Angstroms.
Claim 7
Dependent Claim
42 words
The method of claim 1 wherein said aluminum-silicon alloy layer is composed of between about 1-4% silicon and is deposited to a preferred thickness of between about 5000 to 20,000 Angstroms and is annealed after deposition at greater than about 400° C.
Claim 8
Dependent Claim
33 words
The method of claim 1 wherein said aluminum-silicon layer is reactive ion etched whereby all aluminum is removed and whereby said silicon nodules are formed on the surface of said silicon nitride layer.
Claim 9
Dependent Claim
23 words
The method of claim 1 wherein said set of narrow trenches is etched to a depth of between about 3000 to 6000 Angstroms.
Claim 10
Dependent Claim
36 words
The method of claim 1 wherein said channel-stop implantation uses boron ions with a dosage of between about 1 E 13 to 1 E 14 atoms/cm 2 and energy of between about 10 to 50 KeV.
Claim 11
Independent Claim
335 words
The method of field oxidation of an integrated circuit wherein said field oxidation has a non-recessed surface and wherein said field oxidation has a small bird's beak comprising: providing an insulating layer over the surface of a silicon substrate; etching through portions of said insulating layer not covered by a mask pattern to said silicon substrate so as to provide an opening exposing the portion of said silicon substrate that will form the said field oxidation; etching a first trench into said exposed portion of said silicon substrate; depositing a layer of silicon nitride over said insulating layer and within said first trench in said silicon substrate; depositing a layer of an aluminum-silicon alloy overlying said silicon nitride layer; etching away said aluminum-silicon layer whereby silicon nodules are formed on the surface of said silicon nitride layer; oxidizing said silicon nodules to form silicon dioxide nodules; etching through said silicon nitride layer to said insulating layer where it exists and to said silicon substrate surface where said substrate is exposed within said opening using said silicon dioxide nodules as a mask; etching a set of narrow trenches into said exposed portions of said silicon substrate within said opening using said silicon dioxide nodules as a mask; selectively ion implanting channel-stops through said opening into said substrate underneath said set of trenches; oxidizing said silicon substrate within said set of trenches wherein said silicon substrate is transformed to silicon dioxide and wherein said silicon dioxide expands to fill said set of trenches wherein said field oxidation is formed with a small said bird's beak and whereby said silicon nitride layer and said silicon dioxide nodules within said opening are pushed up to align with said silicon nitride layer and said silicon dioxide nodules on either side of said opening so that the surface of said field oxidation is non-recessed; and removing remaining said insulating layer and said silicon nitride layer wherein said silicon dioxide nodules are also removed completing said field oxidation of said integrated circuit.
Claim 12
Independent Claim
335 words
The method of field oxidation of an integrated circuit wherein said field oxidation has a non-recessed surface and wherein said field oxidation has a small bird's beak comprising: providing an insulating layer over the surface of a silicon substrate; etching through portions of said insulating layer not covered by a mask pattern to said silicon substrate so as to provide an opening exposing the portion of said silicon substrate that will form the said field oxidation; etching a first trench into said exposed portion of said silicon substrate; depositing a layer of silicon nitride over said insulating layer and within said first trench in said silicon substrate; depositing a layer of an aluminum-silicon alloy overlying said silicon nitride layer; etching away said aluminum-silicon layer whereby silicon nodules are formed on the surface of said silicon nitride layer; oxidizing said silicon nodules to form silicon dioxide nodules; etching through said silicon nitride layer to said insulating layer where it exists and to said silicon substrate surface where said substrate is exposed within said opening using said silicon dioxide nodules as a mask; etching a set of narrow trenches into said exposed portions of said silicon substrate within said opening using said silicon dioxide nodules as a mask; selectively ion implanting channel-stops through said opening into said substrate underneath said set of trenches; oxidizing said silicon substrate within said set of trenches wherein said silicon substrate is transformed to silicon dioxide and wherein said silicon dioxide expands to fill said set of trenches wherein said field oxidation is formed with a small said bird's beak and whereby said silicon nitride layer and said silicon dioxide nodules within said opening are pushed up to align with said silicon nitride layer and said silicon dioxide nodules on either side of said opening so that the surface of said field oxidation is non-recessed; and removing remaining said insulating layer and said silicon nitride layer wherein said silicon dioxide nodules are also removed completing said field oxidation of said integrated circuit.
Claim 13
Dependent Claim
26 words
The method of claim 10 wherein said insulating layer is composed of silicon dioxide and has a preferred thickness of between about 500 to 1000 Angstroms.
Claim 14
Dependent Claim
21 words
The method of claim 10 wherein said first trench is etched to a depth of between about 1000 to 2000 Angstroms.
Claim 15
Dependent Claim
21 words
The method of claim 10 wherein said silicon nitride layer has a preferred thickness of between about 500 to 2000 Angstroms.
Claim 16
Dependent Claim
37 words
The method of claim 10 wherein said aluminum-silicon alloy layer is composed of between about 1-4% silicon and is deposited at greater than about 400° C. to a preferred thickness of between about 5000 to 20,000 Angstroms.
Claim 17
Dependent Claim
42 words
The method of claim 10 wherein said aluminum-silicon alloy layer is composed of between about 1-4% silicon and is deposited to a preferred thickness of between about 5000 to 20,000 Angstroms and is annealed after deposition at greater than about 400° C.
Claim 18
Dependent Claim
33 words
The method of claim 10 wherein said aluminum-silicon layer is reactive ion etched whereby all aluminum is removed and whereby said silicon nodules are formed on the surface of said silicon nitride layer.
Claim 19
Dependent Claim
23 words
The method of claim 10 wherein said set of narrow trenches is etched to a depth of between about 3000 to 6000 Angstroms.
Claim 20
Dependent Claim
36 words
The method of claim 10 wherein said channel-stop implantation uses boron ions with a dosage of between about 1 E 13 to 1 E 14 atoms/cm 2 and energy of between about 10 to 50 KeV.
References Cited (Backward Citations)
JPS55113343A
Cited
US4211582A
Cited
JPS5694646A
Cited
EP0245538A2
Cited
JPS61255040A
Cited
US5204280A
Cited
US5292689A
Cited
US5308786A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-12-19 | 1998-06-20 | 1998-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-19 | 2002-06-20 | 2002-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-19 | 2006-06-20 | 2006-12-20 | $7700.00 | Window Closed / Lapsed |